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[/] [xge_mac/] [trunk/] [tbench/] [verilog/] [tb_xge_mac.sv] - Rev 17

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Rev Log message Author Age Path
17 Fixed deprecated SystemC warnings antanguay 4662d 22h /xge_mac/trunk/tbench/verilog/tb_xge_mac.sv
16 Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim antanguay 4663d 05h /xge_mac/trunk/tbench/verilog/tb_xge_mac.sv
14 Change interface to big endian, added serdes examples to testbench antanguay 5271d 00h /xge_mac/trunk/tbench/verilog/tb_xge_mac.v
12 Change interface to big endian, added serdes examples to testbench antanguay 5271d 00h /xge_mac/trunk/tbench/verilog/tb_xge_mac.v
7 New directory structure. root 5549d 10h /xge_mac/trunk/tbench/verilog/tb_xge_mac.v
6 Updated spec. Added mod[2:0] signals. Timing improvements. antanguay 5825d 17h /xge_mac/trunk/tbench/verilog/tb_xge_mac.v
2 Initial revision antanguay 5831d 21h /xge_mac/trunk/tbench/verilog/tb_xge_mac.v

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