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Subversion Repositories xge_mac

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Rev Log message Author Age Path
31 Add more install info to README.TXT antanguay 2634d 02h /
30 Changes to testbench to support Icarus simulator antanguay 4142d 12h /
29 Adding parameter for max frame size antanguay 4149d 01h /
28 Adding parameter for max frame size antanguay 4149d 01h /
27 Fix octets stats on barrel shift transitions antanguay 4198d 01h /
26 Fix packet count antanguay 4204d 01h /
25 Timing improvements, reduced FIFO size from 1024 to 512 antanguay 4204d 03h /
24 Use FIFO's for statistics clock domain crossing antanguay 4204d 04h /
23 Adding basic packet stats antanguay 4204d 10h /
22 Added prototype system verilog testbench antanguay 4206d 07h /
21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4206d 07h /
20 Updates for Xilinx synthesis antanguay 4496d 02h /
19 Updates for 32/64 bit systems antanguay 4671d 03h /
18 Updates for linux 32-bit antanguay 4671d 23h /
17 Fixed deprecated SystemC warnings antanguay 4674d 07h /
16 Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim antanguay 4674d 14h /
15 Updated for Verilator 3.813 antanguay 4693d 14h /
14 Change interface to big endian, added serdes examples to testbench antanguay 5282d 08h /
13 Change interface to big endian, added serdes examples to testbench antanguay 5282d 09h /
12 Change interface to big endian, added serdes examples to testbench antanguay 5282d 09h /
11 Fixed clock crossing antanguay 5388d 06h /
10 Added details to spec antanguay 5486d 01h /
9 Added old uploaded documents to new repository. root 5560d 13h /
8 Added old uploaded documents to new repository. root 5560d 18h /
7 New directory structure. root 5560d 18h /
6 Updated spec. Added mod[2:0] signals. Timing improvements. antanguay 5837d 02h /
5 Fixed compilation antanguay 5843d 02h /
4 Created antanguay 5843d 05h /
3 This commit was manufactured by cvs2svn to create tag 'initial'. 5843d 06h /
2 Initial revision antanguay 5843d 06h /

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