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Rev Log message Author Age Path
41 Merge remote-tracking branch 'origin.xucpu/master' into svn lcdsgmtr 2659d 17h /
40 Merge commit 'f1258dc' into svn lcdsgmtr 2659d 17h /
39 Further additions to board template. lcdsgmtr 2976d 17h /
38 Building up the bare board with its components. lcdsgmtr 2976d 17h /
37 Write main board file as framework to follow. lcdsgmtr 2977d 19h /
36 Creating the new structure.
Adding entities and their architecture in separate directories.		 lcdsgmtr 2977d 19h /
35 Main work: create interface for instruction fetch, instruction cache,
instruction cache control and system bus.		 lcdsgmtr 2977d 19h /
34 Added makefile for this system.
Added board simulator file for this system.
Removed simple errors from main system.		 lcdsgmtr 2977d 19h /
33 Removal of simple compilation errors. lcdsgmtr 2977d 19h /
32 Added necessary red tape for implementing all these components. lcdsgmtr 2977d 19h /
31 Definition of system architecture library.
Definition of top level system architecture.
Main components used in top level system definition.		 lcdsgmtr 2977d 19h /
30 First implementation of cache memory. lcdsgmtr 2977d 19h /
29 All kinds of changes in different configurations. lcdsgmtr 2977d 19h /
28 Added project files for different systems. lcdsgmtr 3129d 20h /
27 When loading the 32k memory, do not let the process stop by a file that is
shorter, also make sure that the process is stopped if the file should be
longer.		 lcdsgmtr 3129d 20h /
26 Added test data for 32k memory.
Added GTKW configuration file.		 lcdsgmtr 3131d 19h /
25 Problem with memory: created conditional generate based upon data width
instead of address width.		 lcdsgmtr 3131d 19h /
24 Starting tracing through the component hierarchy initialisation. lcdsgmtr 3131d 19h /
23 Currently moved test bench to 10 bit address.
Created spreadsheet for filling memory with random data.
When testing, memory is apparently not initialised.		 lcdsgmtr 3131d 19h /
22 Update on makefile, because some parts are in other files. lcdsgmtr 3131d 19h /

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