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Rev Log message Author Age Path
41 Merge remote-tracking branch 'origin.xucpu/master' into svn lcdsgmtr 2673d 00h /xucpu/
40 Merge commit 'f1258dc' into svn lcdsgmtr 2673d 00h /xucpu/
39 Further additions to board template. lcdsgmtr 2989d 23h /xucpu/
38 Building up the bare board with its components. lcdsgmtr 2989d 23h /xucpu/
37 Write main board file as framework to follow. lcdsgmtr 2991d 02h /xucpu/
36 Creating the new structure.
Adding entities and their architecture in separate directories.		 lcdsgmtr 2991d 02h /xucpu/
35 Main work: create interface for instruction fetch, instruction cache,
instruction cache control and system bus.		 lcdsgmtr 2991d 02h /xucpu/
34 Added makefile for this system.
Added board simulator file for this system.
Removed simple errors from main system.		 lcdsgmtr 2991d 02h /xucpu/
33 Removal of simple compilation errors. lcdsgmtr 2991d 02h /xucpu/
32 Added necessary red tape for implementing all these components. lcdsgmtr 2991d 02h /xucpu/
31 Definition of system architecture library.
Definition of top level system architecture.
Main components used in top level system definition.		 lcdsgmtr 2991d 02h /xucpu/
30 First implementation of cache memory. lcdsgmtr 2991d 02h /xucpu/
29 All kinds of changes in different configurations. lcdsgmtr 2991d 02h /xucpu/
28 Added project files for different systems. lcdsgmtr 3143d 03h /xucpu/
27 When loading the 32k memory, do not let the process stop by a file that is
shorter, also make sure that the process is stopped if the file should be
longer.		 lcdsgmtr 3143d 03h /xucpu/
26 Added test data for 32k memory.
Added GTKW configuration file.		 lcdsgmtr 3145d 02h /xucpu/
25 Problem with memory: created conditional generate based upon data width
instead of address width.		 lcdsgmtr 3145d 02h /xucpu/
24 Starting tracing through the component hierarchy initialisation. lcdsgmtr 3145d 02h /xucpu/
23 Currently moved test bench to 10 bit address.
Created spreadsheet for filling memory with random data.
When testing, memory is apparently not initialised.		 lcdsgmtr 3145d 02h /xucpu/
22 Update on makefile, because some parts are in other files. lcdsgmtr 3145d 02h /xucpu/
21 Since all BRAM is unified in one component, this testbench is not necessary
anymore.		 lcdsgmtr 3145d 02h /xucpu/
20 Update RAM package to allow for 15-bit address.
Update test bench to use address width parameter.		 lcdsgmtr 3145d 02h /xucpu/
19 Makefile for building memory block testbench. lcdsgmtr 3145d 02h /xucpu/
18 Ignore work files from GHDL. lcdsgmtr 3145d 02h /xucpu/
17 Moving the generic block ram component piece by piece to a better
implementation.		 lcdsgmtr 3145d 02h /xucpu/
16 Re-write of memory in function of initial array memory blocks. lcdsgmtr 3145d 02h /xucpu/
15 Unification of all RAM parts into one interface. lcdsgmtr 3145d 02h /xucpu/
14 Simple implementation project. lcdsgmtr 3277d 00h /xucpu/
13 Updated smallest Xilinx configuration. lcdsgmtr 3277d 00h /xucpu/
12 Update Xilinx configurations. lcdsgmtr 3277d 00h /xucpu/

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