URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [txuart.v] - Rev 117

Rev	Log message	Author	Age	Path
117	Updates, to include new README and bench/cpp/Makefile that doesnt depend upon a static VERILATOR_ROOT location.	dgisselq	2768d 04h	/xulalx25soc/trunk/rtl/txuart.v
113	Lots of updates, mostly focused on getting the XuLA board and CPU able to pass a comprehensive test suite. At this point, everything passes and logic usage is down even. Among the few changes includes the "break" bit in the uCC register, used to indicate a switch to supervisor mode occurred as a result of a user break, and the ability for the supervisor to clear the instruction cache.	dgisselq	2861d 06h	/xulalx25soc/trunk/rtl/txuart.v
99	Includes high-speed updates. rxuart and txuart will now run at 200MHz on an Artix-7, so should not impact timing (any more) on the XuLA platform.	dgisselq	2870d 01h	/xulalx25soc/trunk/rtl/txuart.v
88	Adjusted copyright date.	dgisselq	2893d 05h	/xulalx25soc/trunk/rtl/txuart.v
9	Bug fixes, optimizations, etc. as part of building for an actual hardware implementation. Most notably, the speed was lowered from 80MHz down to 76 MHz.	dgisselq	3057d 03h	/xulalx25soc/trunk/rtl/txuart.v
7	Mostly minor changes. Fixed the legal copyright statement in the UART files, adjusted some comments, and made sure that the zipdbg program contained all the latest features from our Vault.	dgisselq	3059d 13h	/xulalx25soc/trunk/rtl/txuart.v
2	A very first, albeit incomplete, build.	dgisselq	3059d 23h	/xulalx25soc/trunk/rtl/txuart.v