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[/] [xulalx25soc/] [trunk/] [xilinx/] - Rev 118

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Rev Log message Author Age Path
118 Lots of changes. The biggest are to the CPU: MPYxHI instructions are now
verified to be working, ILLegal instructions stop at the right location,
the STEP bit no longer self-clears, etc. Other changes cleaned up the
internal documentation and removed parameters that should only have local
scope from the global parameter list. The NEW_INSTRUCTION_SET was also
removed from the CPU, since ... it's been new for too long to really be new
anymore.		 dgisselq 2744d 07h /xulalx25soc/trunk/xilinx/
117 Updates, to include new README and bench/cpp/Makefile that doesnt depend upon
a static VERILATOR_ROOT location.		 dgisselq 2768d 22h /xulalx25soc/trunk/xilinx/
97 Latest working bit file, with all changes attached as of this date. dgisselq 2893d 22h /xulalx25soc/trunk/xilinx/
80 Currently working version: contains both a working DMA controller as well as
a working (as far as I can tell) SD-Card controller (writes not yet tested).		 dgisselq 2899d 18h /xulalx25soc/trunk/xilinx/
22 Added the mkdatev.pl file. (Oops!) dgisselq 3002d 00h /xulalx25soc/trunk/xilinx/
18 Got the bitfile back up to speed at 80 MHz. dgisselq 3055d 22h /xulalx25soc/trunk/xilinx/
15 WORKING VERSION! ... or, at least the memory test works. dgisselq 3057d 17h /xulalx25soc/trunk/xilinx/
12 Modified to match the settings I'm now using within ISE. dgisselq 3057d 20h /xulalx25soc/trunk/xilinx/
7 Mostly minor changes. Fixed the legal copyright statement in the UART files,
adjusted some comments, and made sure that the zipdbg program contained all
the latest features from our Vault.		 dgisselq 3060d 06h /xulalx25soc/trunk/xilinx/
6 Initial file load, likely to be buggy, but the initial load nonetheless. dgisselq 3060d 16h /xulalx25soc/trunk/xilinx/

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