URL https://opencores.org/ocsvn/y80e/y80e/trunk

Subversion Repositories y80e

[/] [y80e/] - Rev 5

Rev	Log message	Author	Age	Path
5	This version is compatible with Zilog Z80 CPU Instructions RES/SET (ii+d),r is unsupported Nonstandard NEG and others ED-prefixed are also unsupported	bsa	4007d 12h	/y80e/
4	Added support for commonly used Z80 undocumented instructions This instructions includes: - operations with halfs of IX and IY registers - undocumented shift instruction SLI (or SLL - Shift Left Logically) Also added emulation of R register	bsa	4007d 12h	/y80e/
3	Complete Y80 implementation. This version of CPU is described in book 'Microprocessor Design Using Verilog HDL' by Monte Dalryple from Systemyde. control.v file completed by me and author of CPU permits me to publish this project.	bsa	4007d 12h	/y80e/
2	Completed Y80 from Systemyde w/o anything else	bsa	4007d 12h	/y80e/
1	The project and the structure was created	root	4008d 01h	/y80e/