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https://opencores.org/ocsvn/lq057q3dc02/lq057q3dc02/trunk
Subversion Repositories lq057q3dc02
[/] - Rev 36
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Last modification
- Rev 36, 2008-11-07 01:39:26 GMT
- Author: jwdonal
- Log message:
- converted dcm_sys_to_lcd source file from verilog to VHDL so users don't have to have mixed-language simulation support. Aren't I so nice?? ;-)
