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Last modification

  • Rev 477, 2011-01-15 05:48:25 GMT
  • Author: julius
  • Log message:
    ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
    Changed cache sizes of both instruction and data cache of reference design to 4kB each.

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