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Last modification

  • Rev 46, 2019-05-17 14:41:06 GMT
  • Author: fransschreuder
  • Log message:
    New Vivado version, changed regmap clock, added byte enable to regmap
    * Updated wupper for Vivado 2018.1
    * Byte enable on registermap is now supported
    * Fixed i2c mux reset (inversion) on VC709 board
    * Regmap is now running on 25 MHz for better timing, this was 41.6 MHz
    * registers can now be disabled at build time using the generate statement in the .yaml file
Path
/virtex7_pcie_dma/trunk/documentation/bibliography.tex
/virtex7_pcie_dma/trunk/documentation/design.tex
/virtex7_pcie_dma/trunk/documentation/et_template/template.tex
/virtex7_pcie_dma/trunk/documentation/figures/dma_core_structure.png
/virtex7_pcie_dma/trunk/documentation/figures/Endless_DMA_impression.pdf
/virtex7_pcie_dma/trunk/documentation/figures/felix_PCIeEngine_to_hostBuffer_interface.odg
/virtex7_pcie_dma/trunk/documentation/figures/pcie_core_basic.png
/virtex7_pcie_dma/trunk/documentation/figures/pcie_core_config1.pdf
/virtex7_pcie_dma/trunk/documentation/figures/pcie_core_config2.pdf
/virtex7_pcie_dma/trunk/documentation/figures/pcie_core_config3.pdf
/virtex7_pcie_dma/trunk/documentation/figures/pcie_core_pf0_bar.png
/virtex7_pcie_dma/trunk/documentation/figures/wb_compatible.pdf
/virtex7_pcie_dma/trunk/documentation/figures/wupper_structure.odg
/virtex7_pcie_dma/trunk/documentation/introduction.tex
/virtex7_pcie_dma/trunk/documentation/registermap.tex
/virtex7_pcie_dma/trunk/documentation/registers-1.0.html
/virtex7_pcie_dma/trunk/documentation/supportedtools.tex
/virtex7_pcie_dma/trunk/documentation/versionhistory.tex
/virtex7_pcie_dma/trunk/documentation/wupper.pdf
/virtex7_pcie_dma/trunk/documentation/wupper.tex
/virtex7_pcie_dma/trunk/documentation/xilinx_core.tex
/virtex7_pcie_dma/trunk/firmware/scripts/Wupper/vivado_import_kintexultrascale.tcl
/virtex7_pcie_dma/trunk/firmware/scripts/Wupper/vivado_import_virtex7.tcl
/virtex7_pcie_dma/trunk/firmware/sources/application/xadc_drp.vhd
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/clk_wiz_40.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/clk_wiz_regmap.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/fifo4KB_256bit.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/fifo16KB_256bit.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/fifo128KB_256bit.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/I2C_RDFifo.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/I2C_WRFifo.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/pcie3_ultrascale_7038.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/pcie3_ultrascale_7039.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/system_management_wiz_0.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/wishbone_memory.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/wishbone_to_wupper_fifo.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/wupper_to_wishbone_fifo.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/clk_wiz_regmap.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/fifo4KB_256bit.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/fifo16KB_256bit.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/fifo128KB_256bit.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/I2C_RDFifo.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/I2C_WRFifo.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/pcie_x8_gen3_3_0.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/wishbone_memory.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/wishbone_to_wupper_fifo.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/wupper_to_wishbone_fifo.xci
/virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/xadc_wiz_0.xci
/virtex7_pcie_dma/trunk/firmware/sources/packages/pcie_package.vhd
/virtex7_pcie_dma/trunk/firmware/sources/pcie/dma_control.vhd
/virtex7_pcie_dma/trunk/firmware/sources/pcie/dma_read_write.vhd
/virtex7_pcie_dma/trunk/firmware/sources/pcie/intr_ctrl.vhd
/virtex7_pcie_dma/trunk/firmware/sources/pcie/pcie_ep_wrap.vhd
/virtex7_pcie_dma/trunk/firmware/sources/pcie/pcie_init.vhd
/virtex7_pcie_dma/trunk/firmware/sources/pcie/pcie_slow_clock.vhd
/virtex7_pcie_dma/trunk/firmware/sources/pcie/wupper.vhd
/virtex7_pcie_dma/trunk/firmware/sources/pcie/wupper_core.vhd
/virtex7_pcie_dma/trunk/firmware/sources/shared/housekeeping.vhd
/virtex7_pcie_dma/trunk/firmware/sources/shared/wupper_oc_top.vhd
/virtex7_pcie_dma/trunk/firmware/sources/templates/dma_control.vhd.template
/virtex7_pcie_dma/trunk/firmware/sources/templates/pcie_package.vhd.template
/virtex7_pcie_dma/trunk/software/regmap/regmap/regmap-struct.h
/virtex7_pcie_dma/trunk/software/regmap/regmap/regmap-symbol.h
/virtex7_pcie_dma/trunk/software/regmap/src/regmap-symbol.c
/virtex7_pcie_dma/trunk/software/wuppercodegen/wuppercodegen/classes.py
/virtex7_pcie_dma/trunk/WupperCodeGenScripts/registers-1.0.yaml

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