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[/] [adv_debug_sys/] [trunk/] [Hardware/] [jtag/] [tap/] [rtl/] [verilog/] - Rev 32

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Last modification

  • Rev 32, 2010-01-18 01:55:16 GMT
  • Author: nyawn
  • Log message:
    Added a hi-speed mode via a change in protocol in the adv_dbg_if core. This should provide an order-of-magnitude speed improvement for some USB JTAG cables. Updated adv_jtag_bridge to match. Updated adv_dbg_if testbenches. Updated documents to reflect the new hi-speed mode. Added alternate USB-Blaster driver based on libftdi, donated by Xianfeng Zeng. Various bugfixes.
Path
/adv_debug_sys/trunk/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/bench/full_system/wave.do
/adv_debug_sys/trunk/Hardware/adv_dbg_if/bench/full_system/xsv_fpga_defines.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/bench/full_system/xsv_fpga_top.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/bench/README_testbench.txt
/adv_debug_sys/trunk/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/bench/simulated_system/cpu_behavioral.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/bench/simulated_system/timescale.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/bench/simulated_system/wave.do
/adv_debug_sys/trunk/Hardware/adv_dbg_if/bench/simulated_system/wb_model_defines.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/bench/simulated_system/wb_slave_behavioral.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/doc/AdvancedDebugInterface.pdf
/adv_debug_sys/trunk/Hardware/adv_dbg_if/doc/src/AdvancedDebugInterface.odt
/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
/adv_debug_sys/trunk/Hardware/altera_virtual_jtag/rtl/vhdl/altera_virtual_jtag.vhd
/adv_debug_sys/trunk/Hardware/jtag/tap/rtl/verilog/tap_defines.v
/adv_debug_sys/trunk/Hardware/jtag/tap/rtl/verilog/tap_top.v
/adv_debug_sys/trunk/Hardware/xilinx_internal_jtag/rtl/verilog/xilinx_internal_jtag.v
/adv_debug_sys/trunk/Software/adv_jtag_bridge/adv_dbg_commands.c
/adv_debug_sys/trunk/Software/adv_jtag_bridge/adv_jtag_bridge.c
/adv_debug_sys/trunk/Software/adv_jtag_bridge/adv_jtag_bridge.h
/adv_debug_sys/trunk/Software/adv_jtag_bridge/bsdl.c
/adv_debug_sys/trunk/Software/adv_jtag_bridge/bsdl_parse.c
/adv_debug_sys/trunk/Software/adv_jtag_bridge/cable_common.c
/adv_debug_sys/trunk/Software/adv_jtag_bridge/cable_usbblaster.c
/adv_debug_sys/trunk/Software/adv_jtag_bridge/cable_usbblaster_ftdi.c
/adv_debug_sys/trunk/Software/adv_jtag_bridge/cable_xpc_dlc9.c
/adv_debug_sys/trunk/Software/adv_jtag_bridge/chain_commands.c
/adv_debug_sys/trunk/Software/adv_jtag_bridge/dbg_api.c
/adv_debug_sys/trunk/Software/adv_jtag_bridge/doc/adv_jtag_bridge.pdf
/adv_debug_sys/trunk/Software/adv_jtag_bridge/doc/src/adv_jtag_bridge.odt
/adv_debug_sys/trunk/Software/adv_jtag_bridge/errcodes.c
/adv_debug_sys/trunk/Software/adv_jtag_bridge/legacy_dbg_commands.c
/adv_debug_sys/trunk/Software/adv_jtag_bridge/Makefile
/adv_debug_sys/trunk/Software/adv_jtag_bridge/or32_selftest.c
/adv_debug_sys/trunk/Software/adv_jtag_bridge/or32_selftest.h
/adv_debug_sys/trunk/Software/adv_jtag_bridge/rsp-server.c
/adv_debug_sys/trunk/Software/adv_jtag_bridge/sim_lib/Makefile
/adv_debug_sys/trunk/Software/adv_jtag_bridge/sim_rtl/dbg_comm.v
/adv_debug_sys/trunk/Software/adv_jtag_bridge/sim_rtl/dbg_comm_vpi.v

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