OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [include/] - Rev 503

Rev

Directory listing | View Log | Compare with Previous | RSS feed

Last modification

  • Rev 503, 2011-03-13 22:49:48 GMT
  • Author: julius
  • Log message:
    ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.