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[/] [socgen/] - Rev 106

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Last modification

Rev 106, 2012-03-08 22:06:53 GMT
Author: jt_eaton
Log message:
checked in orp_soc project step 2

Path
/socgen/trunk/Makefile
/socgen/trunk/projects/opencores.org/orp_soc/doc/pdf/journal.pdf
/socgen/trunk/projects/opencores.org/orp_soc/doc/src/journal.html
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/top.rtl
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/xml/generic_orpsocv2_ra_ti_ua.design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/xml/generic_orpsocv2_ra_ti_ua.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/default
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/default/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/default/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/default/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/jtag-basic
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/jtag-basic/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/jtag-basic/sram.vmem
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/jtag-basic/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/jtag-basic/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/xml/generic_orpsocv2_ra_ti_ua_tb.design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/xml/generic_orpsocv2_ra_ti_ua_tb.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/bin
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/bin/Makefile
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/doc
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/doc/copyright.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/doc/html
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/doc/orig6502.txt
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/doc/png
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/doc/Readme.txt
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/doc/spec.odt
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/doc/T6502_doc.txt
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/doc/timing
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/ip-xact
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/ip-xact/Nexys2_orpsocv2_default.designCfg.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/rtl
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/rtl/verilog
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/rtl/verilog/top.disp
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/rtl/verilog/top.disp_0
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/rtl/verilog/top.disp_1
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/rtl/verilog/top.disp_2
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/rtl/verilog/top.ext
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/rtl/verilog/top.gpio
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/rtl/verilog/top.io_mux
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/rtl/verilog/top.irq
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/rtl/verilog/top.jabc
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/rtl/verilog/top.ps2
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/rtl/verilog/top.rs_uart
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/rtl/verilog/top.soc_or
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/rtl/verilog/top.uart
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/rtl/verilog/top.vga
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/rtl/xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/rtl/xml/Nexys2_orpsocv2_default.design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/rtl/xml/Nexys2_orpsocv2_default.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/sim
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/sim/bin
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/sim/bin/Makefile
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/sim/icarus
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/sim/icarus/uart-simple
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/sim/icarus/uart-simple/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/sim/icarus/uart-simple/sram.vmem
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/sim/icarus/uart-simple/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/sim/icarus/uart-simple/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/sim/verilog
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/sim/verilog/tb.ext
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/sim/xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/sim/xml/Nexys2_orpsocv2_tb.design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/sim/xml/Nexys2_orpsocv2_tb.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/soc
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/syn
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/syn/ise
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/syn/ise/Nexys2_orpsocv2_default
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/syn/ise/Nexys2_orpsocv2_default/bsdl
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/syn/ise/Nexys2_orpsocv2_default/bsdl/xc3s1200e_fg320_1532.bsd
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/doc
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/doc/copyright.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/ip-xact
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/ip-xact/orpsocv2_ra_ti_ua.designCfg.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/arbiter
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/arbiter/arbiter.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/arbiter/arbiter_bytebus.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/arbiter/arbiter_dbus.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/arbiter/arbiter_ibus.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/arbiter/README
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/dbg_cpu_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/dbg_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/dbg_if
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/dbg_if/dbg_cpu.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/dbg_if/dbg_cpu_registers.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/dbg_if/dbg_crc32_d1.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/dbg_if/dbg_register.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/dbg_if/dbg_top.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/dbg_if/dbg_wb.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/dbg_wb_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/intgen
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/intgen/intgen.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/or1200
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/or1200/or1200_alu.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/or1200/or1200_amultp2_32x32.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/or1200/or1200_cfgr.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/or1200/or1200_cpu.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/or1200/or1200_ctrl.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/or1200/or1200_dc_ram.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/or1200/or1200_dc_tag.v
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/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/or1200/or1200_fpu_post_norm_mul.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/or1200/or1200_fpu_pre_norm_addsub.v
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/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/or1200/timescale.v
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/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/sim/verilog/timescale.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/sim/verilog/top.rtl
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/sim/xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/sim/xml/orpsocv2_ra_ti_ua_tb.design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/sim/xml/orpsocv2_ra_ti_ua_tb.xml
/socgen/trunk/tools/bin/Makefile.root
/socgen/trunk/tools/install/Ubuntu_11.10/Makefile
/socgen/trunk/tools/utils/bin2abs.c
/socgen/trunk/tools/utils/Makefile

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