OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] - Rev 114

Rev

Directory listing | View Log | Compare with Previous | RSS feed

Last modification

  • Rev 114, 2012-04-16 20:54:53 GMT
  • Author: jt_eaton
  • Log message:
    moved or1200 connectivity out of verilog and into ip-xact
    added or1200_boot block
    removed force of 00 on lowest iwb_addr bits
Path
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/rtl/xml/or1k_spr_rtl.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/ip-xact/cde_jtag_classic_rpc_in_reg.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/ip-xact/cde_jtag_rpc_reg.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/sim/cde_sram_be.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/syn/cde_sram_be.v
/socgen/trunk/projects/opencores.org/or1k/bin/compile
/socgen/trunk/projects/opencores.org/or1k/bin/Makefile.or32
/socgen/trunk/projects/opencores.org/or1k/doc/pdf/journal.pdf
/socgen/trunk/projects/opencores.org/or1k/doc/src/journal.html
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/or1200_defines.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/or1200_monitor.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/or1200_monitor_defines.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/or1200_spram_32_bw.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/or1200_tpram_32x32.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/top.dbg
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_dbg.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_dbg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-basic/wave.sav
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-div/wave.sav
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-mul/wave.sav
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-qmem/wave.sav
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/xml/or1200_dbg_tb.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/or1200_dc_ram.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/or1200_dc_tag.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/or1200_ic_ram.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/or1200_ic_tag.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml/or1200_cache_data.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml/or1200_cache_inst.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cfgr/rtl/verilog/top.def
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cfgr/rtl/xml/or1200_cfgr_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/or1200_boot.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/or1200_genpc.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/top.dbg
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_dbg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_lsu/rtl/verilog/defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_lsu/rtl/verilog/top.def
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_lsu/rtl/xml/or1200_lsu_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/top.data
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/top.inst
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml/or1200_mmu_data.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml/or1200_mmu_inst.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/rtl/verilog/defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/rtl/verilog/defines.asic
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/rtl/verilog/or1200_amultp2_32x32.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/rtl/verilog/or1200_gmultp2_32x32.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/rtl/verilog/top.def
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/rtl/xml/or1200_mult_mac_asic.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/rtl/xml/or1200_pic_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/rtl/xml/or1200_pm_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/verilog/defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/verilog/top.def
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/verilog/top.split
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/xml/or1200_qmem_def.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/xml/or1200_qmem_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/xml/or1200_qmem_split.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_rf/rtl/verilog/or1200_rfram_generic.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_rf/rtl/verilog/top.def
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_rf/rtl/xml/or1200_rf_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/rtl/xml/or1200_sb_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sprs/rtl/verilog/top.def
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/rtl/xml/or1200_tt_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/verilog/defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/verilog/top.def
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/xml/or1200_wb_biu_def.xml
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-cbasic/Makefile
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-dctest/Makefile
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-div/Makefile
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-div/or1200-div.c
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-float/Makefile
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-mmu/Makefile
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-mul/Makefile
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-mul/or1200-mul.c
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-simple/Makefile
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_memory/rtl/xml/wb_memory_def.xml
/socgen/trunk/tools/bin/Makefile.root

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.