OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] - Rev 101

Rev

Directory listing | View Log | Compare with Previous | RSS feed

Last modification

  • Rev 101, 2011-12-12 03:33:51 GMT
  • Author: jt_eaton
  • Log message:
    Added new designs for minsoc release candidate
    convert tool set to parse proper ip-xact

    THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT
Path
/socgen/trunk/Makefile
/socgen/trunk/projects/opencores.org/Busdefs/bin/repeater
/socgen/trunk/projects/opencores.org/Busdefs/ip/clock/busdeftypes/clock_def.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/clock/rtl/xml/clock_rtl.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/enable/busdeftypes/enable_def.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/enable/rtl/xml/enable_rtl.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/ext_bus/busdeftypes/ext_bus.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/ext_bus/rtl/xml/ext_bus_rtl.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/jtag/busdeftypes/jtag_def.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/jtag/rtl/xml/jtag_rpc_rtl.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/micro_bus/busdeftypes/micro_bus_def.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/micro_bus/rtl/xml/micro_bus_rtl.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/bin
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/bin/Makefile
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/busdeftypes
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/busdeftypes/or1k_cpu.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/busdeftypes/or1k_dbg.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/busdeftypes/or1k_spr.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/doc
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/doc/copyright.v
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/doc/html
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/doc/png
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/doc/timing
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/ip-xact
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/rtl
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/rtl/xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/rtl/xml/or1k_cpu_rtl.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/rtl/xml/or1k_dbg_rtl.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/rtl/xml/or1k_spr_rtl.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/sim
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/sim/bin
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/sim/bin/Makefile
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/sim/icarus
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/sim/verilog
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/sim/xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/syn
/socgen/trunk/projects/opencores.org/Busdefs/ip/pad/busdeftypes/pad_def.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/pad/rtl/xml/pad_mux.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/pad/rtl/xml/pad_ring.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/pad/rtl/xml/pad_rtl.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/ps2/busdeftypes/ps2_def.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/ps2/rtl/xml/ps2_rtl.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/reset/busdeftypes/reset_def.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/reset/rtl/xml/reset_rtl.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/uart/busdeftypes/uart_def.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/uart/rtl/xml/uart_rtl.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/vga/busdeftypes/vga_def.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/vga/rtl/xml/vga_rtl.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/wishbone/busdeftypes/wishbone_def.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/wishbone/rtl/xml/wishbone_rtl.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_diff_testmux.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_diff_testmux.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_gater.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_gater.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_multiplier.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_multiplier.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_sys.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_sys.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_testmux.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_testmux.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/rtl/verilog/sim/cde_divider_def.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/rtl/verilog/syn/cde_divider_def.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/rtl/xml/cde_divider_def.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/rtl/xml/cde_divider_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/rtl/verilog/cde_fifo_def.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/rtl/xml/cde_fifo_def.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/rtl/xml/cde_fifo_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_in_reg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_in_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_reg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_def.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_rpc_in_reg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_rpc_in_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_rpc_reg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_rpc_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/xml/cde_jtag_tb.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/xml/cde_jtag_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/rtl/verilog/sim/cde_lifo_def.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/rtl/verilog/syn/cde_lifo_def.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/rtl/xml/cde_lifo_def.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/rtl/xml/cde_lifo_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_diff_dig.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_diff_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_in_dig.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_in_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_od_dig.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_od_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_out_dig.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_out_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_se_dig.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_se_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/rtl/xml/cde_prescale_def.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/rtl/xml/cde_prescale_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/xml/cde_reset_asyncdisable.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/xml/cde_reset_asyncdisable.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/xml/cde_reset_def.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/xml/cde_reset_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/rtl/xml/cde_serial_rcvr.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/rtl/xml/cde_serial_rcvr.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/rtl/xml/cde_serial_xmit.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/rtl/xml/cde_serial_xmit.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/sim/cde_sram_def.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/syn/cde_sram_def.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_def.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_dp.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_dp.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/xml/cde_sync_def.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/xml/cde_sync_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/xml/cde_sync_with_hysteresis.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/xml/cde_sync_with_hysteresis.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/xml/cde_sync_with_reset.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/xml/cde_sync_with_reset.xml
/socgen/trunk/projects/opencores.org/fpga_or1200
/socgen/trunk/projects/opencores.org/fpga_or1200/bin
/socgen/trunk/projects/opencores.org/fpga_or1200/bin/Makefile.6502
/socgen/trunk/projects/opencores.org/fpga_or1200/ip
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/bin
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/bin/Makefile
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/doc
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/doc/copyright.v
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/doc/html
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/doc/orig6502.txt
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/doc/png
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/doc/Readme.txt
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/doc/spec.odt
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/doc/T6502_doc.txt
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/doc/timing
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/ip-xact
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/ip-xact/Nexys2_minsoc_def.designCfg.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/ip-xact/Nexys2_minsoc_default.designCfg.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/verilog
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/verilog/top.disp
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/verilog/top.disp_0
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/verilog/top.disp_1
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/verilog/top.disp_2
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/verilog/top.ext
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/verilog/top.gpio
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/verilog/top.io_mux
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/verilog/top.irq
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/verilog/top.jabc
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/verilog/top.ps2
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/verilog/top.rs_uart
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/verilog/top.soc_or
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/verilog/top.uart
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/verilog/top.vga
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_def.design.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_def.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_default.design.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_default.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_uart.design.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_uart.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/bin
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/bin/Makefile
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/icarus
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/icarus/uart-nocache_emb
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/icarus/uart-nocache_emb/dmp_define
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/icarus/uart-nocache_emb/test_define
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/icarus/uart-nocache_emb/wave.sav
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/verilog
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/verilog/tb.ext
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/xml/Nexys2_minsoc_tb.design.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/xml/Nexys2_minsoc_tb.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/soc
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/syn
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/syn/ise
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/syn/ise/Nexys2_minsoc_uart
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/syn/ise/Nexys2_minsoc_uart/bsdl
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/syn/ise/Nexys2_minsoc_uart/bsdl/xc3s1200e_fg320_1532.bsd
/socgen/trunk/projects/opencores.org/fpga_or1200/sw
/socgen/trunk/projects/opencores.org/fpga_or1200/sw/font
/socgen/trunk/projects/opencores.org/fpga_or1200/sw/font/font.asm
/socgen/trunk/projects/opencores.org/fpga_or1200/sw/font/Makefile
/socgen/trunk/projects/opencores.org/fpga_or1200/sw/startup
/socgen/trunk/projects/opencores.org/fpga_or1200/sw/startup/Makefile
/socgen/trunk/projects/opencores.org/fpga_or1200/sw/startup/startup.asm
/socgen/trunk/projects/opencores.org/fpga_or1200/sw/vga_font
/socgen/trunk/projects/opencores.org/fpga_or1200/sw/vga_font/Makefile
/socgen/trunk/projects/opencores.org/fpga_or1200/sw/vga_font/vga_font.asm
/socgen/trunk/projects/opencores.org/fpga_or1200/sw/vga_startup_screen
/socgen/trunk/projects/opencores.org/fpga_or1200/sw/vga_startup_screen/Makefile
/socgen/trunk/projects/opencores.org/fpga_or1200/sw/vga_startup_screen/vga_startup_screen.asm
/socgen/trunk/projects/opencores.org/fpga_or1200/x
/socgen/trunk/projects/opencores.org/logic/ip/disp_io/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/logic/ip/disp_io/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/logic/ip/disp_io/rtl/xml/disp_io_def.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/disp_io/rtl/xml/disp_io_def.xml
/socgen/trunk/projects/opencores.org/logic/ip/disp_io/sim/xml/disp_io_tb.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/disp_io/sim/xml/disp_io_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/flash_memcontrl/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/logic/ip/flash_memcontrl/rtl/xml/flash_memcontrl_def.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/flash_memcontrl/rtl/xml/flash_memcontrl_def.xml
/socgen/trunk/projects/opencores.org/logic/ip/flash_memcontrl/sim/verilog/tb.ext
/socgen/trunk/projects/opencores.org/logic/ip/flash_memcontrl/sim/xml/flash_memcontrl_tb.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/flash_memcontrl/sim/xml/flash_memcontrl_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/micro_bus/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/logic/ip/micro_bus/rtl/xml/micro_bus_byte.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/micro_bus/rtl/xml/micro_bus_byte.xml
/socgen/trunk/projects/opencores.org/logic/ip/micro_bus/rtl/xml/micro_bus_def.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/micro_bus/rtl/xml/micro_bus_def.xml
/socgen/trunk/projects/opencores.org/logic/ip/micro_bus/rtl/xml/micro_bus_exp5.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/micro_bus/rtl/xml/micro_bus_exp5.xml
/socgen/trunk/projects/opencores.org/logic/ip/micro_bus/rtl/xml/micro_bus_exp6.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/micro_bus/rtl/xml/micro_bus_exp6.xml
/socgen/trunk/projects/opencores.org/logic/ip/micro_bus/rtl/xml/micro_bus_exp9.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/micro_bus/rtl/xml/micro_bus_exp9.xml
/socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/rtl/xml/ps2_interface_def.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/rtl/xml/ps2_interface_def.xml
/socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/sim/verilog/tb.ext
/socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/sim/xml/ps2_interface_mouse_tb.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/sim/xml/ps2_interface_mouse_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/sim/xml/ps2_interface_tb.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/sim/xml/ps2_interface_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/serial_rcvr/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/logic/ip/serial_rcvr/rtl/xml/serial_rcvr_def.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/serial_rcvr/rtl/xml/serial_rcvr_def.xml
/socgen/trunk/projects/opencores.org/logic/ip/serial_rcvr/rtl/xml/serial_rcvr_fifo.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/serial_rcvr/rtl/xml/serial_rcvr_fifo.xml
/socgen/trunk/projects/opencores.org/logic/ip/serial_rcvr/sim/xml/serial_rcvr_fifo_tb.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/serial_rcvr/sim/xml/serial_rcvr_fifo_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/serial_rcvr/sim/xml/serial_rcvr_tb.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/serial_rcvr/sim/xml/serial_rcvr_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/logic/ip/uart/rtl/verilog/top.body.rx
/socgen/trunk/projects/opencores.org/logic/ip/uart/rtl/verilog/top.body.rxtx
/socgen/trunk/projects/opencores.org/logic/ip/uart/rtl/verilog/top.body.tx
/socgen/trunk/projects/opencores.org/logic/ip/uart/rtl/xml/uart_def.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/rtl/xml/uart_def.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/rtl/xml/uart_rx.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/rtl/xml/uart_rx.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/rtl/xml/uart_rxtx.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/rtl/xml/uart_rxtx.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/rtl/xml/uart_tx.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/rtl/xml/uart_tx.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/sim/verilog/tb.ext
/socgen/trunk/projects/opencores.org/logic/ip/uart/sim/xml/uart_rxtx_tb.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/sim/xml/uart_rxtx_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/sim/xml/uart_rx_tb.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/sim/xml/uart_rx_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/sim/xml/uart_tb.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/sim/xml/uart_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/sim/xml/uart_tx_tb.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/sim/xml/uart_tx_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/usb_epp/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/logic/ip/usb_epp/rtl/xml/usb_epp_def.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/usb_epp/rtl/xml/usb_epp_def.xml
/socgen/trunk/projects/opencores.org/logic/ip/usb_epp/sim/xml/usb_epp_tb.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/usb_epp/sim/xml/usb_epp_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/vga_char_ctrl/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/logic/ip/vga_char_ctrl/rtl/verilog/char_gen
/socgen/trunk/projects/opencores.org/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl_def.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl_def.xml
/socgen/trunk/projects/opencores.org/logic/ip/vga_char_ctrl/sim/xml/vga_char_ctrl_tb.design.xml
/socgen/trunk/projects/opencores.org/logic/ip/vga_char_ctrl/sim/xml/vga_char_ctrl_tb.xml
/socgen/trunk/projects/opencores.org/or1k
/socgen/trunk/projects/opencores.org/or1k/bin
/socgen/trunk/projects/opencores.org/or1k/bin/repeater
/socgen/trunk/projects/opencores.org/or1k/ip
/socgen/trunk/projects/opencores.org/or1k/ip/or1200
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/bin
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/doc
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/doc/copyright.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/ip-xact
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/ip-xact/or1200_dbg.designcfg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_dbg.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_dbg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/bin
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/bin
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/doc
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/doc/copyright.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/ip-xact
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/4KB_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/8KB_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/data_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/data_isa_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/dc_fsm
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/dc_ram
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/dc_tag
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/ic_fsm
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/ic_ram
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/ic_tag
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/inst_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/inst_isa_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/spram_32x24
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/spram_128x32
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/spram_256x21
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/spram_512x20
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/spram_1024x32
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/spram_1024x32_bw
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/spram_2048x32_bw
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/top.data
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/top.inst
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml/or1200_cache_data.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml/or1200_cache_data.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml/or1200_cache_inst.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml/or1200_cache_inst.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/sim
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/sim/bin
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/bin
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/doc
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/doc/copyright.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/ip-xact
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/ip-xact/or1200_cpu_dbg.designcfg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/alu
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/amultp2_32x32
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cfgr
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/ctrl
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/dpram_32x32
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/dpram_256x32
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/except
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/freeze
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/genpc
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/gmultp2_32x32
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/if
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/isa_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/isa_defines_dbg
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/lsu
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/mem2reg
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/mult_mac
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/operandmuxes
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/reg2mem
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/rf
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/rfram_generic
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/sprs
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/top.dbg
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/tpram_32x32
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/wbmux
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_dbg.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_dbg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/sim
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/sim/bin
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_du
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_du/bin
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_du/doc
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_du/doc/copyright.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_du/ip-xact
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_du/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_du/rtl
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_du/rtl/verilog
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_du/rtl/verilog/defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_du/rtl/verilog/du
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_du/rtl/verilog/top
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_du/rtl/xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_du/rtl/xml/or1200_du_def.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_du/rtl/xml/or1200_du_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_du/sim
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_du/sim/bin
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/bin
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/doc
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/doc/copyright.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/ip-xact
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/data_isa_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/data_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/data_isa_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/dmmu_tlb
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/immu_tlb
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/inst_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/inst_isa_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/spram_64x14
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/spram_64x22
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/spram_64x24
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/top.data
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/top.inst
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml/or1200_mmu_data.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml/or1200_mmu_data.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml/or1200_mmu_inst.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml/or1200_mmu_inst.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/sim
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/sim/bin
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/bin
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/doc
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/doc/copyright.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/ip-xact
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/rtl
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/rtl/verilog
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/rtl/verilog/defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/rtl/verilog/pic
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/rtl/xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/rtl/xml/or1200_pic_def.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/rtl/xml/or1200_pic_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/sim
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/sim/bin
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/bin
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/doc
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/doc/copyright.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/ip-xact
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/rtl
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/rtl/verilog
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/rtl/verilog/defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/rtl/verilog/pm
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/rtl/xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/rtl/xml/or1200_pm_def.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/rtl/xml/or1200_pm_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/sim
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/sim/bin
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/bin
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/doc
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/doc/copyright.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/ip-xact
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/verilog
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/verilog/defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/verilog/spram_2048x32
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/xml/or1200_qmem_def.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/xml/or1200_qmem_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/sim
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/sim/bin
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/bin
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/doc
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/doc/copyright.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/ip-xact
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/rtl
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/rtl/verilog
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/rtl/verilog/defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/rtl/verilog/sb
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/rtl/verilog/sb_fifo
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/rtl/verilog/top
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/rtl/xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/rtl/xml/or1200_sb_def.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/rtl/xml/or1200_sb_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/sim
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/sim/bin
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/bin
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/doc
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/doc/copyright.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/ip-xact
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/rtl
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/rtl/verilog
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/rtl/verilog/defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/rtl/verilog/top
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/rtl/verilog/tt
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/rtl/xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/rtl/xml/or1200_tt_def.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/rtl/xml/or1200_tt_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/sim
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/sim/bin
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/bin
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/doc
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/doc/copyright.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/ip-xact
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/verilog
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/verilog/defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/verilog/top.data
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/verilog/top.inst
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/verilog/wb_biu_d
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/verilog/wb_biu_i
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/xml/or1200_wb_biu_d.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/xml/or1200_wb_biu_d.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/xml/or1200_wb_biu_i.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/xml/or1200_wb_biu_i.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/sim
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/sim/bin
/socgen/trunk/projects/opencores.org/or1k/sw
/socgen/trunk/projects/opencores.org/targets/bin/repeater
/socgen/trunk/projects/opencores.org/targets/ip/Basys/lib/ip/cde_jtag/rtl/views/syn/cde_jtag_def.v
/socgen/trunk/projects/opencores.org/targets/ip/Nexys2/lib/ip/cde_jtag/rtl/views/syn/cde_jtag_def.v
/socgen/trunk/projects/opencores.org/Testbench/ip/clock_gen/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/clock_gen/rtl/views/sim/clock_gen_def.v
/socgen/trunk/projects/opencores.org/Testbench/ip/clock_gen/rtl/views/syn/clock_gen_def.v
/socgen/trunk/projects/opencores.org/Testbench/ip/clock_gen/rtl/xml/clock_gen_def.design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/clock_gen/rtl/xml/clock_gen_def.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/io_probe/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/io_probe/rtl/xml/io_probe_def.design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/io_probe/rtl/xml/io_probe_def.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/io_probe/rtl/xml/io_probe_in.design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/io_probe/rtl/xml/io_probe_in.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/jtag_model/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/jtag_model/rtl/xml/jtag_model_def.design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/jtag_model/rtl/xml/jtag_model_def.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/micro_bus16_model/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/micro_bus16_model/rtl/verilog/sim/top
/socgen/trunk/projects/opencores.org/Testbench/ip/micro_bus16_model/rtl/verilog/syn/top
/socgen/trunk/projects/opencores.org/Testbench/ip/micro_bus16_model/rtl/xml/micro_bus16_model_def.design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/micro_bus16_model/rtl/xml/micro_bus16_model_def.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/micro_bus_model/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/micro_bus_model/rtl/verilog/sim/top
/socgen/trunk/projects/opencores.org/Testbench/ip/micro_bus_model/rtl/verilog/syn/top
/socgen/trunk/projects/opencores.org/Testbench/ip/micro_bus_model/rtl/xml/micro_bus_model_def.design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/micro_bus_model/rtl/xml/micro_bus_model_def.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/mt45w8mw12/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/mt45w8mw12/rtl/verilog/sim/top
/socgen/trunk/projects/opencores.org/Testbench/ip/mt45w8mw12/rtl/verilog/syn/top
/socgen/trunk/projects/opencores.org/Testbench/ip/mt45w8mw12/rtl/xml/mt45w8mw12_def.design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/mt45w8mw12/rtl/xml/mt45w8mw12_def.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/ps2_host/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/ps2_host/rtl/verilog/sim/top
/socgen/trunk/projects/opencores.org/Testbench/ip/ps2_host/rtl/verilog/syn/top
/socgen/trunk/projects/opencores.org/Testbench/ip/ps2_host/rtl/xml/ps2_host_def.design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/ps2_host/rtl/xml/ps2_host_def.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/ps2_model/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/ps2_model/rtl/verilog/top.rtl
/socgen/trunk/projects/opencores.org/Testbench/ip/ps2_model/rtl/xml/ps2_model_def.design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/ps2_model/rtl/xml/ps2_model_def.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/uart_host/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/uart_host/rtl/verilog/sim/top
/socgen/trunk/projects/opencores.org/Testbench/ip/uart_host/rtl/verilog/syn/top
/socgen/trunk/projects/opencores.org/Testbench/ip/uart_host/rtl/xml/uart_host_def.design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/uart_host/rtl/xml/uart_host_def.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/uart_model/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/uart_model/rtl/verilog/top.rtl
/socgen/trunk/projects/opencores.org/Testbench/ip/uart_model/rtl/xml/uart_model_def.design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/uart_model/rtl/xml/uart_model_def.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/bin
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/bin/Makefile
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/doc
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/doc/copyright.v
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/doc/html
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/doc/png
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/doc/timing
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/ip-xact
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/rtl
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/rtl/verilog
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/rtl/verilog/sim
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/rtl/verilog/sim/top
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/rtl/verilog/sim/top.8bit
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/rtl/verilog/syn
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/rtl/verilog/syn/top
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/rtl/verilog/syn/top.8bit
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/rtl/xml
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/rtl/xml/wb_master_model_8bit.design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/rtl/xml/wb_master_model_8bit.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/rtl/xml/wb_master_model_def.design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/rtl/xml/wb_master_model_def.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/sim
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/sim/xml
/socgen/trunk/projects/opencores.org/Testbench/ip/wb_master_model/soc
/socgen/trunk/projects/opencores.org/Testbench/ip/wishbone_monitor
/socgen/trunk/projects/opencores.org/Testbench/ip/wishbone_monitor/bin
/socgen/trunk/projects/opencores.org/Testbench/ip/wishbone_monitor/bin/Makefile
/socgen/trunk/projects/opencores.org/Testbench/ip/wishbone_monitor/doc
/socgen/trunk/projects/opencores.org/Testbench/ip/wishbone_monitor/doc/copyright.v
/socgen/trunk/projects/opencores.org/Testbench/ip/wishbone_monitor/doc/html
/socgen/trunk/projects/opencores.org/Testbench/ip/wishbone_monitor/doc/png
/socgen/trunk/projects/opencores.org/Testbench/ip/wishbone_monitor/doc/timing
/socgen/trunk/projects/opencores.org/Testbench/ip/wishbone_monitor/ip-xact
/socgen/trunk/projects/opencores.org/Testbench/ip/wishbone_monitor/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/wishbone_monitor/rtl
/socgen/trunk/projects/opencores.org/Testbench/ip/wishbone_monitor/rtl/verilog
/socgen/trunk/projects/opencores.org/Testbench/ip/wishbone_monitor/rtl/verilog/sim
/socgen/trunk/projects/opencores.org/Testbench/ip/wishbone_monitor/rtl/verilog/sim/top
/socgen/trunk/projects/opencores.org/Testbench/ip/wishbone_monitor/rtl/verilog/syn
/socgen/trunk/projects/opencores.org/Testbench/ip/wishbone_monitor/rtl/verilog/syn/top
/socgen/trunk/projects/opencores.org/Testbench/ip/wishbone_monitor/rtl/xml
/socgen/trunk/projects/opencores.org/Testbench/ip/wishbone_monitor/rtl/xml/wishbone_monitor_def.design.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/wishbone_monitor/rtl/xml/wishbone_monitor_def.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/wishbone_monitor/sim
/socgen/trunk/projects/opencores.org/Testbench/ip/wishbone_monitor/sim/xml
/socgen/trunk/projects/opencores.org/Testbench/ip/wishbone_monitor/soc
/socgen/trunk/projects/opencores.org/wishbone
/socgen/trunk/projects/opencores.org/wishbone/bin
/socgen/trunk/projects/opencores.org/wishbone/bin/fizzim
/socgen/trunk/projects/opencores.org/wishbone/bin/repeater
/socgen/trunk/projects/opencores.org/wishbone/doc
/socgen/trunk/projects/opencores.org/wishbone/doc/wbspec_b2.pdf
/socgen/trunk/projects/opencores.org/wishbone/doc/wbspec_b3.pdf
/socgen/trunk/projects/opencores.org/wishbone/doc/wbspec_b4.pdf
/socgen/trunk/projects/opencores.org/wishbone/ip
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/bin
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/bin/Makefile
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/doc
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/doc/copyright.v
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/doc/html
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/doc/png
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/doc/timing
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/ip-xact
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/rtl
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/rtl/verilog
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/rtl/verilog/defines
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/rtl/xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/rtl/xml/wb_ram_def.design.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/rtl/xml/wb_ram_def.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/sim
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/sim/bin
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/sim/bin/Makefile
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/sim/icarus
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/sim/icarus/default
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/sim/icarus/default/dmp_define
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/sim/icarus/default/test_define
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/sim/icarus/default/wave.sav
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/sim/verilog
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/sim/verilog/tb.ext
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/sim/xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/sim/xml/wb_ram_tb.design.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/sim/xml/wb_ram_tb.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/soc
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/syn
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/bin
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/bin/Makefile
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/doc
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/doc/copyright.v
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/doc/html
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/doc/png
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/doc/timing
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/ip-xact
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/rtl
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/rtl/verilog
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/rtl/verilog/defines
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/rtl/verilog/tc_mi_to_st
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/rtl/verilog/tc_si_to_mt
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/rtl/xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/rtl/xml/wb_traffic_cop_def.design.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/rtl/xml/wb_traffic_cop_def.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/bin
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/bin/Makefile
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/icarus
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/icarus/default
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/icarus/default/dmp_define
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/icarus/default/test_define
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/icarus/default/wave.sav
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/xml/wb_traffic_cop_tb.design.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/xml/wb_traffic_cop_tb.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/bin
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/bin/Makefile
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/doc
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/doc/copyright.v
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/doc/html
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/doc/png
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/doc/timing
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/ip-xact
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/variants
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/variants/wb_uart16550
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/variants/wb_uart16550/defines.v
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/variants/wb_uart16550_orpsocv2
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/variants/wb_uart16550_orpsocv2/defines.v
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/verilog
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/verilog/debug_if
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/verilog/defines
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/verilog/raminfr
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/verilog/receiver
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/verilog/regs
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/verilog/rfifo
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/verilog/sync_flops
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/verilog/tfifo
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/verilog/transmitter
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/verilog/wb_fsm
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_bus16_big.design.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_bus16_big.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_bus16_lit.design.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_bus16_lit.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_bus32_big.design.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_bus32_big.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_bus32_lit.design.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_bus32_lit.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_def.design.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_def.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/bin
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/bin/Makefile
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus16_big_default
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus16_big_default/dmp_define
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus16_big_default/test_define
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus16_big_default/wave.sav
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus16_lit_default
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus16_lit_default/dmp_define
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus16_lit_default/test_define
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus16_lit_default/wave.sav
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus32_big_default
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus32_big_default/dmp_define
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus32_big_default/test_define
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus32_big_default/wave.sav
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus32_lit_default
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus32_lit_default/dmp_define
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus32_lit_default/test_define
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus32_lit_default/wave.sav
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/default
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/default/dmp_define
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/default/test_define
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/default/wave.sav
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/verilog
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/verilog/tb.ext
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/xml/wb_uart16550_bus16_big_tb.design.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/xml/wb_uart16550_bus16_big_tb.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/xml/wb_uart16550_bus16_lit_tb.design.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/xml/wb_uart16550_bus16_lit_tb.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/xml/wb_uart16550_bus32_big_tb.design.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/xml/wb_uart16550_bus32_big_tb.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/xml/wb_uart16550_bus32_lit_tb.design.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/xml/wb_uart16550_bus32_lit_tb.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/xml/wb_uart16550_tb.design.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/xml/wb_uart16550_tb.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/soc
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/syn
/socgen/trunk/projects/opencores.org/wishbone/soc
/socgen/trunk/projects/opencores.org/wishbone/soc/library.soc
/socgen/trunk/projects/opencores.org/wishbone/sw
/socgen/trunk/projects/opencores.org/xfer
/socgen/trunk/projects/opencores.org/xfer/bin
/socgen/trunk/projects/opencores.org/xfer/bin/repeater
/socgen/trunk/projects/opencores.org/xfer/ip
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/doc
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/doc/copyright.v
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/ip-xact
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/verilog
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/verilog/bytefifo
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/verilog/crc32
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/verilog/jsp_biu
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/verilog/jsp_module
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/verilog/or1k_biu
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/verilog/or1k_defines
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/verilog/or1k_module
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/verilog/or1k_status_reg
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/verilog/syncflop
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/verilog/syncreg
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/verilog/top
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/verilog/wb_biu
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/verilog/wb_cpu2_jsp_defines
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/verilog/wb_cpu_defines
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/verilog/wb_defines
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/verilog/wb_module
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/verilog/wishbone_defines
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/xml
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/xml/adv_dbg_if_wb.design.xml
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/xml/adv_dbg_if_wb.xml
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/xml/adv_dbg_if_wb_cpu.design.xml
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/xml/adv_dbg_if_wb_cpu.xml
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/xml/adv_dbg_if_wb_cpu2_jsp.design.xml
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/xml/adv_dbg_if_wb_cpu2_jsp.xml
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/sim
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/sim/bin
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/doc
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/doc/copyright.v
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/ip-xact
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/ip-xact/minsoc_def.designCfg.xml
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/rtl
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/rtl/verilog
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/rtl/verilog/defines
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/rtl/verilog/top
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/rtl/xml
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/rtl/xml/minsoc_def.design.xml
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/rtl/xml/minsoc_def.xml
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/sim
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/sim/bin
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/sim/bin/Makefile
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/sim/icarus
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/sim/icarus/default
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/sim/icarus/default/dmp_define
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/sim/icarus/default/test_define
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/sim/icarus/default/wave.sav
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/sim/xml
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/sim/xml/minsoc_tb.design.xml
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/sim/xml/minsoc_tb.xml
/socgen/trunk/projects/opencores.org/xfer/sw
/socgen/trunk/projects/opencores.org/xfer/sw/backend
/socgen/trunk/projects/opencores.org/xfer/sw/backend/board.h
/socgen/trunk/projects/opencores.org/xfer/sw/backend/gcc-opt.mk
/socgen/trunk/projects/opencores.org/xfer/sw/backend/or1200.h
/socgen/trunk/projects/opencores.org/xfer/sw/backend/orp.ld
/socgen/trunk/projects/opencores.org/xfer/sw/drivers
/socgen/trunk/projects/opencores.org/xfer/sw/drivers/interrupts.c
/socgen/trunk/projects/opencores.org/xfer/sw/drivers/Makefile
/socgen/trunk/projects/opencores.org/xfer/sw/drivers/uart.c
/socgen/trunk/projects/opencores.org/xfer/sw/drivers/uart.h
/socgen/trunk/projects/opencores.org/xfer/sw/support
/socgen/trunk/projects/opencores.org/xfer/sw/support/except.S
/socgen/trunk/projects/opencores.org/xfer/sw/support/int.c
/socgen/trunk/projects/opencores.org/xfer/sw/support/int.h
/socgen/trunk/projects/opencores.org/xfer/sw/support/Makefile
/socgen/trunk/projects/opencores.org/xfer/sw/support/Makefile.inc
/socgen/trunk/projects/opencores.org/xfer/sw/support/reset.S
/socgen/trunk/projects/opencores.org/xfer/sw/support/support.c
/socgen/trunk/projects/opencores.org/xfer/sw/support/support.h
/socgen/trunk/projects/opencores.org/xfer/sw/support/tick.c
/socgen/trunk/projects/opencores.org/xfer/sw/support/tick.h
/socgen/trunk/projects/opencores.org/xfer/sw/uart
/socgen/trunk/projects/opencores.org/xfer/sw/uart/Makefile
/socgen/trunk/projects/opencores.org/xfer/sw/uart/uart.c
/socgen/trunk/projects/opencores.org/xfer/sw/uart2
/socgen/trunk/projects/opencores.org/xfer/sw/uart2/Makefile
/socgen/trunk/projects/opencores.org/xfer/sw/uart2/uart2.c
/socgen/trunk/tools/sys/build_geda
/socgen/trunk/tools/sys/build_registers
/socgen/trunk/tools/sys/build_sim_filelists
/socgen/trunk/tools/sys/build_syn_filelists
/socgen/trunk/tools/sys/build_verilog
/socgen/trunk/tools/sys/build_verilogLibraryFile
/socgen/trunk/tools/sys/soc_builder
/socgen/trunk/tools/sys/soc_generate
/socgen/trunk/tools/sys/soc_link_child
/socgen/trunk/tools/utils
/socgen/trunk/tools/utils/bin2abs.c
/socgen/trunk/tools/utils/bin2c.c
/socgen/trunk/tools/utils/bin2flimg.c
/socgen/trunk/tools/utils/bin2hex.c
/socgen/trunk/tools/utils/bin2srec.c
/socgen/trunk/tools/utils/bin2vmem.c
/socgen/trunk/tools/utils/Makefile
/socgen/trunk/tools/utils/or32-idecode
/socgen/trunk/tools/utils/or32-idecode/ansidecl.h
/socgen/trunk/tools/utils/or32-idecode/bfd.h
/socgen/trunk/tools/utils/or32-idecode/dis-asm.h
/socgen/trunk/tools/utils/or32-idecode/example_input
/socgen/trunk/tools/utils/or32-idecode/Makefile
/socgen/trunk/tools/utils/or32-idecode/or32-dis.c
/socgen/trunk/tools/utils/or32-idecode/or32-opc.c
/socgen/trunk/tools/utils/or32-idecode/or32.h
/socgen/trunk/tools/utils/or32-idecode/symcat.h

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.