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[/] [socgen/] [trunk/] - Rev 103

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Last modification

  • Rev 103, 2012-02-13 00:37:45 GMT
  • Author: jt_eaton
  • Log message:
    added user guide
    resynced to local repository
Path
/socgen/trunk/doc/pdf/guide_users.pdf
/socgen/trunk/doc/src/guides/guide_users.html
/socgen/trunk/Makefile
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/rtl/xml/or1k_cpu_rtl.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_def.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_irq_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/xml/Nexys2_T6502_tb.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/xml/Basys_mrisc_loop.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/sim/xml/Basys_soc_mrisc_io_mouse_tb.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse_default.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse_mouse.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/sim/xml/Nexys2_soc_mrisc_io_mouse_tb.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/verilog/top.vga
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_def.design.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_uart.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/xml/Nexys2_minsoc_tb.design.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/xml/Nexys2_minsoc_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/sim/xml/io_ext_mem_interface_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_gpio/sim/xml/io_gpio_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_def.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_gpio.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_mouse.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_gpio_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_mouse_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_pic/sim/xml/io_pic_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/rtl/xml/io_ps2_def.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/rtl/xml/io_ps2_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/rtl/xml/io_ps2_mouse.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/rtl/xml/io_ps2_mouse.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/xml/io_ps2_mouse_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/xml/io_ps2_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_timer/sim/xml/io_timer_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_def.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_rx.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_rx.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_rxtx.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_rxtx.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_tx.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_tx.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_rxtx_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_rx_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_tx_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_utimer/sim/xml/io_utimer_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vga/rtl/xml/io_vga_def.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vga/rtl/xml/io_vga_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vga/sim/xml/io_vga_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vic/sim/xml/io_vic_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/disp_io/sim/xml/disp_io_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/flash_memcontrl/sim/xml/flash_memcontrl_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/rtl/xml/ps2_interface_def.xml
/socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/sim/xml/ps2_interface_mouse_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/sim/xml/ps2_interface_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/serial_rcvr/rtl/xml/serial_rcvr_def.xml
/socgen/trunk/projects/opencores.org/logic/ip/serial_rcvr/rtl/xml/serial_rcvr_fifo.xml
/socgen/trunk/projects/opencores.org/logic/ip/serial_rcvr/sim/xml/serial_rcvr_fifo_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/serial_rcvr/sim/xml/serial_rcvr_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/sim/xml/uart_rxtx_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/sim/xml/uart_rx_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/sim/xml/uart_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/sim/xml/uart_tx_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/usb_epp/sim/xml/usb_epp_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl_def.xml
/socgen/trunk/projects/opencores.org/logic/ip/vga_char_ctrl/sim/xml/vga_char_ctrl_tb.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502/rtl/xml/T6502_def.design.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502/rtl/xml/T6502_def.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502/sim/xml/T6502_tb.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502_cpu/sim/xml/T6502_cpu_tb.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502_cpu_alu_logic/sim/xml/T6502_cpu_alu_logic_tb.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_dbg.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_dbg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml/or1200_cache_data.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml/or1200_cache_inst.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_dbg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_du/rtl/xml/or1200_du_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/top.data
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/top.inst
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml/or1200_mmu_data.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml/or1200_mmu_inst.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/xml/or1200_qmem_def.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/mrisc/rtl/xml/mrisc_def.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/mrisc/sim/xml/mrisc_tb.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_io_tb.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_tb.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/soc_mrisc/rtl/xml/soc_mrisc_io.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/soc_mrisc/sim/xml/soc_mrisc_io_tb.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/ip-xact/wb_ram_def.designCfg.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/rtl/xml/wb_ram_def.design.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/rtl/xml/wb_ram_def.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/sim/xml/wb_ram_tb.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/rtl/verilog/tc_si_to_mt
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/rtl/xml/wb_traffic_cop_def.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/xml/wb_traffic_cop_tb.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/xml/wb_uart16550_bus16_big_tb.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/xml/wb_uart16550_bus16_lit_tb.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/xml/wb_uart16550_bus32_big_tb.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/xml/wb_uart16550_bus32_lit_tb.xml
/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/xml/wb_uart16550_tb.xml
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/xml/adv_dbg_if_wb.xml
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/xml/adv_dbg_if_wb_cpu.xml
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/rtl/verilog/top.rtl
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/rtl/xml/minsoc_def.design.xml
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/rtl/xml/minsoc_def.xml
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/sim/xml/minsoc_tb.design.xml
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/sim/xml/minsoc_tb.xml
/socgen/trunk/tools/install/Ubuntu_11.10/Makefile
/socgen/trunk/tools/or32-elf
/socgen/trunk/tools/or32-elf/Makefile
/socgen/trunk/tools/or32-elf/or32-elf-1.0rc1-x86.tar.bz2
/socgen/trunk/tools/or32-elf/or32-elf-linux-x86.tar.bz2
/socgen/trunk/tools/or32-elf/Readme.txt
/socgen/trunk/tools/sys/build_sim_filelists
/socgen/trunk/tools/sys/build_verilog

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