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[/] [socgen/] [trunk/] - Rev 115

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Last modification

Rev 115, 2012-04-28 20:41:01 GMT
Author: jt_eaton
Log message:
split or1200_cpu up into all ip-xact components
removed dead files

Path
/socgen/trunk/doc/geda
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/rtl/xml/or1k_cpu_rtl.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/bin
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/doc
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/doc/copyright.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/ip-xact
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/ip-xact/cde_mult_asic_tb.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/ip-xact/cde_mult_generic_64_tb.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/ip-xact/cde_mult_generic_tb.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/ip-xact/cde_mult_ord_r4_tb.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/ip-xact/cde_mult_serial_tb.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/verilog
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/verilog/or1200_amultp2_32x32.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/verilog/or1200_gmultp2_32x32.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/verilog/ord_r4.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/verilog/top.asic
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/verilog/top.generic
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/verilog/top.ord_r4
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/verilog/top.serial
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_asic.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_generic.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_ord_r4.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_serial.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/bin
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/bin/Makefile
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus/asic
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus/asic/dmp_define
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus/asic/test_define
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus/asic/wave.sav
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus/generic
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus/generic/dmp_define
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus/generic/test_define
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus/generic/wave.sav
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus/generic_64
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus/generic_64/dmp_define
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus/generic_64/test_define
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus/generic_64/wave.sav
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus/ord_r4
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus/ord_r4/dmp_define
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus/ord_r4/test_define
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus/ord_r4/wave.sav
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus/serial
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus/serial/dmp_define
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus/serial/test_define
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/icarus/serial/wave.sav
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/verilog
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/verilog/synthesys
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/verilog/top
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/verilog/top.64
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_asic_tb.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_asic_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_generic_64_tb.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_generic_64_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_generic_tb.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_generic_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_ord_r4_tb.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_ord_r4_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_serial_tb.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_serial_tb.xml
/socgen/trunk/projects/opencores.org/or1k/doc/pdf/journal.pdf
/socgen/trunk/projects/opencores.org/or1k/doc/src/journal.html
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/clkgen
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/or1200
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/or1200_monitor.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/or1200_monitor_defines.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_clkgen.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_dbg.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_dbg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-no_code_sprs_sys/test_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-no_code_sprs_sys/wave.sav
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/xml/or1200_dbg_tb.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/ip-xact/or1200_cache_data.designCfg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/ip-xact/or1200_cache_inst.designCfg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/4KB_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/8KB_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/data_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/data_isa_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/dc_fsm
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/dc_ram
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/dc_tag
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/ic_fsm
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/ic_ram
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/ic_tag
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/inst_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/inst_isa_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/or1200_dc_fsm.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/or1200_dc_ram.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/or1200_dc_tag.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/or1200_ic_ram.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/or1200_ic_tag.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/spram_32x24
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/spram_128x32
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/spram_256x21
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/spram_512x20
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/spram_1024x32
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/spram_1024x32_bw
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/spram_2048x32_bw
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/top.data
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/top.inst
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml/or1200_cache_data.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml/or1200_cache_data.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml/or1200_cache_inst.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml/or1200_cache_inst.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cfgr
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/ip-xact/or1200_cpu_dbg.designCfg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/alu
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/amultp2_32x32
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cfgr
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_alu
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_boot
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_cfgr
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_ctrl
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_du
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_except
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_freeze
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_genpc
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_if
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_lsu
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_operandmuxes
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_rf
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_sprs
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_sprs.sim
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_spr_mux
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_wbmux
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/ctrl
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/dpram_32x32
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/dpram_256x32
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/except
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/freeze
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/genpc
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/gmultp2_32x32
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/if
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/isa_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/isa_defines_dbg
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/lsu
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/mem2reg
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/mult_mac
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/operandmuxes
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/or1200_alu.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/or1200_boot.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/or1200_ctrl.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/or1200_du.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/or1200_except.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/or1200_freeze.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/or1200_genpc.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/or1200_if.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/or1200_operandmuxes.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/or1200_wbmux.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/ram_generic
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/reg2mem
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/rf
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/rfram_generic
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/sprs
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/top.dbg
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/tpram_32x32
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/wbmux
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_alu.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_boot.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_cfgr.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_ctrl.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_dbg.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_dbg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_def.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_du.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_except.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_freeze.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_genpc.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_if.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_lsu.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_operandmuxes.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_rf.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_sprs.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_spr_mux.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_wbmux.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_du
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_fpu/doc/FPU.pdf
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_fpu/rtl/verilog/top.def
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_fpu/rtl/xml/or1200_fpu_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_lsu
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/ip-xact/or1200_mmu_data.designCfg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/ip-xact/or1200_mmu_inst.designCfg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/data_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/data_isa_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/dmmu_tlb
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/immu_tlb
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/inst_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/inst_isa_defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/or1200_dmmu_tlb.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/or1200_immu_tlb.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/spram_64x14
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/spram_64x22
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/spram_64x24
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/top.data
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/top.inst
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml/or1200_mmu_data.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml/or1200_mmu_data.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml/or1200_mmu_inst.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml/or1200_mmu_inst.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/rtl/verilog/top.def
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/rtl/xml/or1200_mult_mac_asic.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/rtl/xml/or1200_mult_mac_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/ip-xact/or1200_pic_def.designCfg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/rtl/verilog/pic
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/rtl/xml/or1200_pic_def.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/ip-xact/or1200_pm_def.designCfg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/rtl/verilog/pm
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/rtl/xml/or1200_pm_def.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/verilog/spram_2048x32
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/verilog/top.rtl
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_rf
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/ip-xact/or1200_sb_def.designCfg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/rtl/verilog/sb
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/rtl/xml/or1200_sb_def.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sprs
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/ip-xact/or1200_tt_def.designCfg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/rtl/verilog/tt
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/rtl/xml/or1200_tt_def.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/ip-xact/or1200_wb_biu_d.designCfg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/ip-xact/or1200_wb_biu_i.designCfg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/verilog/top.data
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/verilog/top.inst
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/verilog/wb_biu_d
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/verilog/wb_biu_i
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/xml/or1200_wb_biu_d.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/xml/or1200_wb_biu_d.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/xml/or1200_wb_biu_i.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/xml/or1200_wb_biu_i.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/top.rtl
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/rtl/xml/minsoc_def.design.xml
/socgen/trunk/tools/sys/build_geda
/socgen/trunk/tools/sys/build_registers
/socgen/trunk/tools/sys/build_verilog
/socgen/trunk/tools/sys/soc_link_child

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