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[/] [socgen/] [trunk/] [tools/] [simulation/] - Rev 124

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Last modification

  • Rev 124, 2012-12-22 22:10:11 GMT
  • Author: jt_eaton
  • Log message:
    beta release candidate 1
    changed design.xml name
    aligned schema with filesystem
Path
/socgen/trunk/doc/src/drawing/sch/um-100_cde_clock_sys_sym.sch
/socgen/trunk/doc/src/drawing/sch/um-100_cde_jtag_def_sym.sch
/socgen/trunk/doc/src/drawing/sch/um-100_cde_sram_be_sym.sch
/socgen/trunk/doc/src/drawing/sch/um-100_cde_sram_def_sym.sch
/socgen/trunk/doc/src/drawing/sch/um-100_cde_sram_dp_sym.sch
/socgen/trunk/doc/src/drawing/sch/um-150_cde_jtag_rpc_sym.sch
/socgen/trunk/doc/src/drawing/sch/um-150_cde_reset_sym.sch
/socgen/trunk/doc/src/drawing/sch/um-150_cde_sync_sym.sch
/socgen/trunk/doc/src/drawing/sym/cde_clock_diff_testmux.sym
/socgen/trunk/doc/src/drawing/sym/cde_clock_gater.sym
/socgen/trunk/doc/src/drawing/sym/cde_clock_multiplier.sym
/socgen/trunk/doc/src/drawing/sym/cde_clock_sys.sym
/socgen/trunk/doc/src/drawing/sym/cde_clock_testmux.sym
/socgen/trunk/doc/src/drawing/sym/cde_divider_def.sym
/socgen/trunk/doc/src/drawing/sym/cde_fifo_def.sym
/socgen/trunk/doc/src/drawing/sym/cde_jtag_classic_rpc_in_reg.sym
/socgen/trunk/doc/src/drawing/sym/cde_jtag_classic_rpc_reg.sym
/socgen/trunk/doc/src/drawing/sym/cde_jtag_def.sym
/socgen/trunk/doc/src/drawing/sym/cde_jtag_rpc_in_reg.sym
/socgen/trunk/doc/src/drawing/sym/cde_jtag_rpc_reg.sym
/socgen/trunk/doc/src/drawing/sym/cde_lifo_def.sym
/socgen/trunk/doc/src/drawing/sym/cde_mult_generic.sym
/socgen/trunk/doc/src/drawing/sym/cde_mult_ord_r4.sym
/socgen/trunk/doc/src/drawing/sym/cde_mult_serial.sym
/socgen/trunk/doc/src/drawing/sym/cde_pad_in_dig.sym
/socgen/trunk/doc/src/drawing/sym/cde_pad_od_dig.sym
/socgen/trunk/doc/src/drawing/sym/cde_pad_out_dig.sym
/socgen/trunk/doc/src/drawing/sym/cde_pad_se_dig.sym
/socgen/trunk/doc/src/drawing/sym/cde_pad_tri_dig.sym
/socgen/trunk/doc/src/drawing/sym/cde_prescale_def.sym
/socgen/trunk/doc/src/drawing/sym/cde_reset_asyncdisable.sym
/socgen/trunk/doc/src/drawing/sym/cde_reset_def.sym
/socgen/trunk/doc/src/drawing/sym/cde_serial_rcvr.sym
/socgen/trunk/doc/src/drawing/sym/cde_serial_xmit.sym
/socgen/trunk/doc/src/drawing/sym/cde_sram_be.sym
/socgen/trunk/doc/src/drawing/sym/cde_sram_def.sym
/socgen/trunk/doc/src/drawing/sym/cde_sram_dp.sym
/socgen/trunk/doc/src/drawing/sym/cde_sync_def.sym
/socgen/trunk/doc/src/drawing/sym/cde_sync_with_hysteresis.sym
/socgen/trunk/doc/src/drawing/sym/cde_sync_with_reset.sym
/socgen/trunk/doc/src/drawing/sym/io_pad.sym
/socgen/trunk/projects/digilentinc.com/Nexys2/ip-xact/library.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip-xact/libraryCfg.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_clock/ip-xact/componentCfg.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_clock/ip-xact/design.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_jtag/ip-xact/componentCfg.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_jtag/ip-xact/design.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/ip-xact/componentCfg.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/clock/sim
/socgen/trunk/projects/opencores.org/Busdefs/ip/enable/sim
/socgen/trunk/projects/opencores.org/Busdefs/ip/ext_bus/sim
/socgen/trunk/projects/opencores.org/Busdefs/ip/micro_bus/sim
/socgen/trunk/projects/opencores.org/Busdefs/ip/pad/sim
/socgen/trunk/projects/opencores.org/Busdefs/ip/ps2/sim
/socgen/trunk/projects/opencores.org/Busdefs/ip/reset/sim
/socgen/trunk/projects/opencores.org/Busdefs/ip/uart/sim
/socgen/trunk/projects/opencores.org/Busdefs/ip/vga/sim
/socgen/trunk/projects/opencores.org/Busdefs/ip/wishbone/sim
/socgen/trunk/projects/opencores.org/cde/doc/drawing
/socgen/trunk/projects/opencores.org/cde/doc/mk_png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_asyncdisable.png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_clk_diff_testmux.png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_clk_gater.png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_clk_testmux.png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_clock_diff_testmux.png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_clock_sys.png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_divider.png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_jtag.png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_jtag_rpc_reg.png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_jtag_rpc_sym.png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_lifo.png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_lifo_def.png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_mult_ord_r4.png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_pad_out_dig.png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_pad_se_dig.png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_reset.png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_reset_sym.png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_serial_rcvr.png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_serial_xmit.png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_sram.png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_sync.png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_sync_with_hysteresis.png
/socgen/trunk/projects/opencores.org/cde/doc/png/cde_sync_with_reset.png
/socgen/trunk/projects/opencores.org/cde/ip-xact/library.xml
/socgen/trunk/projects/opencores.org/cde/ip-xact/libraryCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_diff_testmux.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_dll.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_gater.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_sys.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_testmux.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/sim/testbenches
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/sim/testbenches/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/sim/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/rtl/xml/cde_divider_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/sim/testbenches
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/sim/testbenches/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/sim/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/rtl/xml/cde_fifo_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/sim/testbenches
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/sim/testbenches/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/sim/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_in_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_def.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_rpc_in_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_rpc_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/icarus/default/wave.sav
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/testbenches
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/testbenches/verilog
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/testbenches/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/testbenches/xml/cde_jtag_bfm.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/testbenches/xml/cde_jtag_def_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/testbenches/xml/cde_jtag_def_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/testbenches/xml/cde_jtag_def_lint.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/testbenches/xml/cde_jtag_def_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/verilog
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/xml/cde_jtag_bfm.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/xml/cde_jtag_def_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/xml/cde_jtag_def_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/xml/cde_jtag_def_lint_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/xml/cde_jtag_def_lint_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/xml/cde_jtag_def_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/xml/cde_jtag_def_tb_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/xml/cde_jtag_def_tb_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/rtl/xml/cde_lifo_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/sim/testbenches
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/sim/testbenches/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/sim/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_generic.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_ord_r4.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_serial.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/verilog
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/verilog/synthesys
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/verilog/top
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/verilog/top.64
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_bfm.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_generic_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_generic_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_generic_lint.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_generic_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_ord_r4_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_ord_r4_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_ord_r4_lint.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_ord_r4_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_serial_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_serial_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_serial_lint.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_serial_tb.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_serial_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/verilog
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_bfm.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_generic_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_generic_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_generic_lint_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_generic_lint_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_generic_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_generic_tb_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_generic_tb_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_ord_r4_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_ord_r4_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_ord_r4_lint_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_ord_r4_lint_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_ord_r4_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_ord_r4_tb_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_ord_r4_tb_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_serial_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_serial_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_serial_lint_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_serial_lint_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_serial_tb.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_serial_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_serial_tb_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_serial_tb_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_in_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_od_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_out_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_se_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_tri_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/sim/testbenches
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/sim/testbenches/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/sim/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/rtl/xml/cde_prescale_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/sim/testbenches
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/sim/testbenches/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/sim/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/xml/cde_reset_asyncdisable.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/xml/cde_reset_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/sim/testbenches
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/sim/testbenches/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/sim/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/rtl/xml/cde_serial_rcvr.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/rtl/xml/cde_serial_xmit.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/sim/testbenches
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/sim/testbenches/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/sim/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/cde_sram.lint
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_be.xml
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/socgen/trunk/tools/yp/index.xml
/socgen/trunk/tools/yp/lib.pm

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