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[/] [socgen/] [trunk/] [tools/] [sys/] - Rev 95

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Last modification

  • Rev 95, 2011-06-21 04:07:18 GMT
  • Author: jt_eaton
  • Log message:
    added first cut at busdefs
    added clock reset enable pads and jtag_rpc
Path
/socgen/trunk/projects/Busdefs
/socgen/trunk/projects/Busdefs/bin
/socgen/trunk/projects/Busdefs/ip
/socgen/trunk/projects/Busdefs/ip/clock
/socgen/trunk/projects/Busdefs/ip/clock/bin
/socgen/trunk/projects/Busdefs/ip/clock/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/clock/busdeftypes
/socgen/trunk/projects/Busdefs/ip/clock/busdeftypes/clock.xml
/socgen/trunk/projects/Busdefs/ip/clock/doc
/socgen/trunk/projects/Busdefs/ip/clock/doc/copyright.v
/socgen/trunk/projects/Busdefs/ip/clock/doc/html
/socgen/trunk/projects/Busdefs/ip/clock/doc/png
/socgen/trunk/projects/Busdefs/ip/clock/doc/timing
/socgen/trunk/projects/Busdefs/ip/clock/rtl
/socgen/trunk/projects/Busdefs/ip/clock/rtl/xml
/socgen/trunk/projects/Busdefs/ip/clock/rtl/xml/clock.xml
/socgen/trunk/projects/Busdefs/ip/clock/sim
/socgen/trunk/projects/Busdefs/ip/clock/sim/bin
/socgen/trunk/projects/Busdefs/ip/clock/sim/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/clock/sim/run
/socgen/trunk/projects/Busdefs/ip/clock/sim/verilog
/socgen/trunk/projects/Busdefs/ip/clock/sim/xml
/socgen/trunk/projects/Busdefs/ip/clock/soc
/socgen/trunk/projects/Busdefs/ip/clock/soc/design.soc
/socgen/trunk/projects/Busdefs/ip/clock/syn
/socgen/trunk/projects/Busdefs/ip/enable
/socgen/trunk/projects/Busdefs/ip/enable/bin
/socgen/trunk/projects/Busdefs/ip/enable/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/enable/busdeftypes
/socgen/trunk/projects/Busdefs/ip/enable/busdeftypes/enable.xml
/socgen/trunk/projects/Busdefs/ip/enable/doc
/socgen/trunk/projects/Busdefs/ip/enable/doc/copyright.v
/socgen/trunk/projects/Busdefs/ip/enable/doc/html
/socgen/trunk/projects/Busdefs/ip/enable/doc/png
/socgen/trunk/projects/Busdefs/ip/enable/doc/timing
/socgen/trunk/projects/Busdefs/ip/enable/rtl
/socgen/trunk/projects/Busdefs/ip/enable/rtl/xml
/socgen/trunk/projects/Busdefs/ip/enable/rtl/xml/enable.xml
/socgen/trunk/projects/Busdefs/ip/enable/sim
/socgen/trunk/projects/Busdefs/ip/enable/sim/bin
/socgen/trunk/projects/Busdefs/ip/enable/sim/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/enable/sim/run
/socgen/trunk/projects/Busdefs/ip/enable/sim/verilog
/socgen/trunk/projects/Busdefs/ip/enable/sim/xml
/socgen/trunk/projects/Busdefs/ip/enable/soc
/socgen/trunk/projects/Busdefs/ip/enable/soc/design.soc
/socgen/trunk/projects/Busdefs/ip/enable/syn
/socgen/trunk/projects/Busdefs/ip/jtag
/socgen/trunk/projects/Busdefs/ip/jtag/bin
/socgen/trunk/projects/Busdefs/ip/jtag/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/jtag/busdeftypes
/socgen/trunk/projects/Busdefs/ip/jtag/busdeftypes/jtag.xml
/socgen/trunk/projects/Busdefs/ip/jtag/doc
/socgen/trunk/projects/Busdefs/ip/jtag/doc/copyright.v
/socgen/trunk/projects/Busdefs/ip/jtag/doc/html
/socgen/trunk/projects/Busdefs/ip/jtag/doc/png
/socgen/trunk/projects/Busdefs/ip/jtag/doc/timing
/socgen/trunk/projects/Busdefs/ip/jtag/rtl
/socgen/trunk/projects/Busdefs/ip/jtag/rtl/xml
/socgen/trunk/projects/Busdefs/ip/jtag/rtl/xml/jtag_rpc.xml
/socgen/trunk/projects/Busdefs/ip/jtag/sim
/socgen/trunk/projects/Busdefs/ip/jtag/sim/bin
/socgen/trunk/projects/Busdefs/ip/jtag/sim/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/jtag/sim/run
/socgen/trunk/projects/Busdefs/ip/jtag/sim/verilog
/socgen/trunk/projects/Busdefs/ip/jtag/sim/xml
/socgen/trunk/projects/Busdefs/ip/jtag/soc
/socgen/trunk/projects/Busdefs/ip/jtag/soc/design.soc
/socgen/trunk/projects/Busdefs/ip/jtag/syn
/socgen/trunk/projects/Busdefs/ip/pad
/socgen/trunk/projects/Busdefs/ip/pad/bin
/socgen/trunk/projects/Busdefs/ip/pad/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/pad/busdeftypes
/socgen/trunk/projects/Busdefs/ip/pad/busdeftypes/pad.xml
/socgen/trunk/projects/Busdefs/ip/pad/doc
/socgen/trunk/projects/Busdefs/ip/pad/doc/copyright.v
/socgen/trunk/projects/Busdefs/ip/pad/doc/html
/socgen/trunk/projects/Busdefs/ip/pad/doc/png
/socgen/trunk/projects/Busdefs/ip/pad/doc/timing
/socgen/trunk/projects/Busdefs/ip/pad/rtl
/socgen/trunk/projects/Busdefs/ip/pad/rtl/xml
/socgen/trunk/projects/Busdefs/ip/pad/rtl/xml/pad.xml
/socgen/trunk/projects/Busdefs/ip/pad/rtl/xml/pad_ring.xml
/socgen/trunk/projects/Busdefs/ip/pad/sim
/socgen/trunk/projects/Busdefs/ip/pad/sim/bin
/socgen/trunk/projects/Busdefs/ip/pad/sim/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/pad/sim/run
/socgen/trunk/projects/Busdefs/ip/pad/sim/verilog
/socgen/trunk/projects/Busdefs/ip/pad/sim/xml
/socgen/trunk/projects/Busdefs/ip/pad/soc
/socgen/trunk/projects/Busdefs/ip/pad/soc/design.soc
/socgen/trunk/projects/Busdefs/ip/pad/syn
/socgen/trunk/projects/Busdefs/ip/reset
/socgen/trunk/projects/Busdefs/ip/reset/bin
/socgen/trunk/projects/Busdefs/ip/reset/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/reset/busdeftypes
/socgen/trunk/projects/Busdefs/ip/reset/busdeftypes/reset.xml
/socgen/trunk/projects/Busdefs/ip/reset/doc
/socgen/trunk/projects/Busdefs/ip/reset/doc/copyright.v
/socgen/trunk/projects/Busdefs/ip/reset/doc/html
/socgen/trunk/projects/Busdefs/ip/reset/doc/png
/socgen/trunk/projects/Busdefs/ip/reset/doc/timing
/socgen/trunk/projects/Busdefs/ip/reset/rtl
/socgen/trunk/projects/Busdefs/ip/reset/rtl/xml
/socgen/trunk/projects/Busdefs/ip/reset/rtl/xml/reset.xml
/socgen/trunk/projects/Busdefs/ip/reset/sim
/socgen/trunk/projects/Busdefs/ip/reset/sim/bin
/socgen/trunk/projects/Busdefs/ip/reset/sim/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/reset/sim/run
/socgen/trunk/projects/Busdefs/ip/reset/sim/verilog
/socgen/trunk/projects/Busdefs/ip/reset/sim/xml
/socgen/trunk/projects/Busdefs/ip/reset/soc
/socgen/trunk/projects/Busdefs/ip/reset/soc/design.soc
/socgen/trunk/projects/Busdefs/ip/reset/syn
/socgen/trunk/projects/Busdefs/soc
/socgen/trunk/projects/Busdefs/soc/library.soc
/socgen/trunk/projects/Busdefs/sw
/socgen/trunk/projects/cde/ip/cde_clock/rtl/gen
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog/sim
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog/sim/cde_clock_diff_testmux.v
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog/sim/cde_clock_gater.v
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog/sim/cde_clock_multiplier.v
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog/sim/cde_clock_sys.v
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog/sim/cde_clock_testmux.v
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog/syn
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog/syn/cde_clock_diff_testmux.v
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog/syn/cde_clock_gater.v
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog/syn/cde_clock_multiplier.v
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog/syn/cde_clock_sys.v
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog/syn/cde_clock_testmux.v
/socgen/trunk/projects/cde/ip/cde_clock/rtl/xml/cde_clock_diff_testmux.xml
/socgen/trunk/projects/cde/ip/cde_clock/rtl/xml/cde_clock_gater.xml
/socgen/trunk/projects/cde/ip/cde_clock/rtl/xml/cde_clock_multiplier.xml
/socgen/trunk/projects/cde/ip/cde_clock/rtl/xml/cde_clock_sys.xml
/socgen/trunk/projects/cde/ip/cde_clock/rtl/xml/cde_clock_testmux.xml
/socgen/trunk/projects/cde/ip/cde_clock_sys
/socgen/trunk/projects/cde/ip/cde_divider/rtl/gen
/socgen/trunk/projects/cde/ip/cde_divider/rtl/verilog
/socgen/trunk/projects/cde/ip/cde_divider/rtl/verilog/sim
/socgen/trunk/projects/cde/ip/cde_divider/rtl/verilog/sim/cde_divider.v
/socgen/trunk/projects/cde/ip/cde_divider/rtl/verilog/syn
/socgen/trunk/projects/cde/ip/cde_divider/rtl/verilog/syn/cde_divider.v
/socgen/trunk/projects/cde/ip/cde_divider/rtl/xml/cde_divider.xml
/socgen/trunk/projects/cde/ip/cde_fifo/rtl/gen
/socgen/trunk/projects/cde/ip/cde_fifo/rtl/verilog
/socgen/trunk/projects/cde/ip/cde_fifo/rtl/verilog/sim
/socgen/trunk/projects/cde/ip/cde_fifo/rtl/verilog/sim/cde_fifo.v
/socgen/trunk/projects/cde/ip/cde_fifo/rtl/verilog/syn
/socgen/trunk/projects/cde/ip/cde_fifo/rtl/verilog/syn/cde_fifo.v
/socgen/trunk/projects/cde/ip/cde_fifo/rtl/xml/cde_fifo.xml
/socgen/trunk/projects/cde/ip/cde_io_mux/rtl/gen
/socgen/trunk/projects/cde/ip/cde_io_mux/rtl/verilog
/socgen/trunk/projects/cde/ip/cde_io_mux/rtl/verilog/sim
/socgen/trunk/projects/cde/ip/cde_io_mux/rtl/verilog/sim/cde_io_mux.v
/socgen/trunk/projects/cde/ip/cde_io_mux/rtl/verilog/syn
/socgen/trunk/projects/cde/ip/cde_io_mux/rtl/verilog/syn/cde_io_mux.v
/socgen/trunk/projects/cde/ip/cde_io_mux/rtl/xml/cde_io_mux.xml
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/gen/sim/cde_jtag_classic_rpc_in_reg.v
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/gen/sim/cde_jtag_classic_rpc_reg.v
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/gen/syn/cde_jtag_classic_rpc_in_reg.v
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/gen/syn/cde_jtag_classic_rpc_reg.v
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/gen/syn/cde_jtag_rpc_reg.v
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/verilog/top.body
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/verilog/top.bsr
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/verilog/top.instr_reg
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/verilog/top.tap
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/verilog/top.tdo
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/xml/cde_jtag.xml
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_in_reg.xml
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_reg.xml
/socgen/trunk/projects/cde/ip/cde_jtag/sim/run/default/wave.sav
/socgen/trunk/projects/cde/ip/cde_jtag/sim/xml/cde_jtag_default.xml
/socgen/trunk/projects/cde/ip/cde_lifo/rtl/gen
/socgen/trunk/projects/cde/ip/cde_lifo/rtl/verilog
/socgen/trunk/projects/cde/ip/cde_lifo/rtl/verilog/sim
/socgen/trunk/projects/cde/ip/cde_lifo/rtl/verilog/sim/cde_lifo.v
/socgen/trunk/projects/cde/ip/cde_lifo/rtl/verilog/syn
/socgen/trunk/projects/cde/ip/cde_lifo/rtl/verilog/syn/cde_lifo.v
/socgen/trunk/projects/cde/ip/cde_lifo/rtl/xml/cde_lifo.xml
/socgen/trunk/projects/cde/ip/cde_pad/rtl/gen
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog/sim
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog/sim/cde_pad_diff_dig.v
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog/sim/cde_pad_in_dig.v
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog/sim/cde_pad_od_dig.v
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog/sim/cde_pad_out_dig.v
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog/sim/cde_pad_se_dig.v
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog/syn
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog/syn/cde_pad_diff_dig.v
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog/syn/cde_pad_in_dig.v
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog/syn/cde_pad_od_dig.v
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog/syn/cde_pad_out_dig.v
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog/syn/cde_pad_se_dig.v
/socgen/trunk/projects/cde/ip/cde_pad/rtl/xml/cde_pad_diff_dig.xml
/socgen/trunk/projects/cde/ip/cde_pad/rtl/xml/cde_pad_in_dig.xml
/socgen/trunk/projects/cde/ip/cde_pad/rtl/xml/cde_pad_od_dig.xml
/socgen/trunk/projects/cde/ip/cde_pad/rtl/xml/cde_pad_out_dig.xml
/socgen/trunk/projects/cde/ip/cde_pad/rtl/xml/cde_pad_se_dig.xml
/socgen/trunk/projects/cde/ip/cde_prescale/rtl/gen
/socgen/trunk/projects/cde/ip/cde_prescale/rtl/verilog
/socgen/trunk/projects/cde/ip/cde_prescale/rtl/verilog/sim
/socgen/trunk/projects/cde/ip/cde_prescale/rtl/verilog/sim/cde_prescale.v
/socgen/trunk/projects/cde/ip/cde_prescale/rtl/verilog/syn
/socgen/trunk/projects/cde/ip/cde_prescale/rtl/verilog/syn/cde_prescale.v
/socgen/trunk/projects/cde/ip/cde_prescale/rtl/xml/cde_prescale.xml
/socgen/trunk/projects/cde/ip/cde_reset/rtl/gen
/socgen/trunk/projects/cde/ip/cde_reset/rtl/verilog
/socgen/trunk/projects/cde/ip/cde_reset/rtl/verilog/sim
/socgen/trunk/projects/cde/ip/cde_reset/rtl/verilog/sim/cde_reset.v
/socgen/trunk/projects/cde/ip/cde_reset/rtl/verilog/sim/cde_reset_asyncdisable.v
/socgen/trunk/projects/cde/ip/cde_reset/rtl/verilog/syn
/socgen/trunk/projects/cde/ip/cde_reset/rtl/verilog/syn/cde_reset.v
/socgen/trunk/projects/cde/ip/cde_reset/rtl/verilog/syn/cde_reset_asyncdisable.v
/socgen/trunk/projects/cde/ip/cde_reset/rtl/xml/cde_reset.xml
/socgen/trunk/projects/cde/ip/cde_reset/rtl/xml/cde_reset_asyncdisable.xml
/socgen/trunk/projects/cde/ip/cde_serial
/socgen/trunk/projects/cde/ip/cde_serial/bin
/socgen/trunk/projects/cde/ip/cde_serial/rtl
/socgen/trunk/projects/cde/ip/cde_serial/rtl/verilog
/socgen/trunk/projects/cde/ip/cde_serial/rtl/verilog/sim
/socgen/trunk/projects/cde/ip/cde_serial/rtl/verilog/sim/cde_serial_rcvr.v
/socgen/trunk/projects/cde/ip/cde_serial/rtl/verilog/sim/cde_serial_xmit.v
/socgen/trunk/projects/cde/ip/cde_serial/rtl/verilog/syn
/socgen/trunk/projects/cde/ip/cde_serial/rtl/verilog/syn/cde_serial_rcvr.v
/socgen/trunk/projects/cde/ip/cde_serial/rtl/verilog/syn/cde_serial_xmit.v
/socgen/trunk/projects/cde/ip/cde_serial/rtl/xml
/socgen/trunk/projects/cde/ip/cde_serial/rtl/xml/cde_serial_rcvr.xml
/socgen/trunk/projects/cde/ip/cde_serial/rtl/xml/cde_serial_xmit.xml
/socgen/trunk/projects/cde/ip/cde_serial/sim
/socgen/trunk/projects/cde/ip/cde_serial/sim/bin
/socgen/trunk/projects/cde/ip/cde_serial/sim/xml
/socgen/trunk/projects/cde/ip/cde_serial/soc
/socgen/trunk/projects/cde/ip/cde_serial/soc/design.soc
/socgen/trunk/projects/cde/ip/cde_serial_rcvr
/socgen/trunk/projects/cde/ip/cde_serial_xmit
/socgen/trunk/projects/cde/ip/cde_sram/rtl/gen
/socgen/trunk/projects/cde/ip/cde_sram/rtl/verilog
/socgen/trunk/projects/cde/ip/cde_sram/rtl/verilog/sim
/socgen/trunk/projects/cde/ip/cde_sram/rtl/verilog/sim/cde_sram.v
/socgen/trunk/projects/cde/ip/cde_sram/rtl/verilog/syn
/socgen/trunk/projects/cde/ip/cde_sram/rtl/verilog/syn/cde_sram.v
/socgen/trunk/projects/cde/ip/cde_sram/rtl/xml/cde_sram.xml
/socgen/trunk/projects/cde/ip/cde_sync/rtl/gen
/socgen/trunk/projects/cde/ip/cde_sync/rtl/verilog
/socgen/trunk/projects/cde/ip/cde_sync/rtl/verilog/sim
/socgen/trunk/projects/cde/ip/cde_sync/rtl/verilog/sim/cde_sync.v
/socgen/trunk/projects/cde/ip/cde_sync/rtl/verilog/sim/cde_sync_with_hysteresis.v
/socgen/trunk/projects/cde/ip/cde_sync/rtl/verilog/sim/cde_sync_with_reset.v
/socgen/trunk/projects/cde/ip/cde_sync/rtl/verilog/syn
/socgen/trunk/projects/cde/ip/cde_sync/rtl/verilog/syn/cde_sync.v
/socgen/trunk/projects/cde/ip/cde_sync/rtl/verilog/syn/cde_sync_with_hysteresis.v
/socgen/trunk/projects/cde/ip/cde_sync/rtl/verilog/syn/cde_sync_with_reset.v
/socgen/trunk/projects/cde/ip/cde_sync/rtl/xml/cde_sync.xml
/socgen/trunk/projects/cde/ip/cde_sync/rtl/xml/cde_sync_with_hysteresis.xml
/socgen/trunk/projects/cde/ip/cde_sync/rtl/xml/cde_sync_with_reset.xml
/socgen/trunk/projects/cde/x
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/rtl/xml/Basys_mrisc.xml
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/rtl/xml/Basys_mrisc_loop.xml
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/sim/xml/Basys_mrisc_loop_sim.xml
/socgen/trunk/projects/fpgas/ip/Basys_soc_mrisc/rtl/xml/Basys_soc_mrisc_io_mouse.xml
/socgen/trunk/projects/fpgas/ip/Basys_soc_mrisc/rtl/xml/Basys_soc_mrisc_io_mouse_mouse.xml
/socgen/trunk/projects/fpgas/ip/Basys_soc_mrisc/sim/xml/Basys_soc_mrisc_io_mouse_mouse_sim.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_soc_mrisc/rtl/verilog/top.ext
/socgen/trunk/projects/fpgas/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse_mouse.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_soc_mrisc/sim/xml/Nexys2_soc_mrisc_io_mouse_mouse_sim.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/rtl/verilog/top.gpio
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_irq_2.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_poll_2.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_irq_2_test.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_kim_2.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_tim_2.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/verilog/tb.ext
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/xml/Nexys2_T6502_io_irq_2_sim.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/xml/Nexys2_T6502_io_poll_2_sim.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/xml/Nexys2_T6502_irq_2_test_sim.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/xml/Nexys2_T6502_kim_2_sim.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/xml/Nexys2_T6502_tim_2_sim.xml
/socgen/trunk/projects/fpgas/targets
/socgen/trunk/projects/io/ip/io_ext_mem_interface/rtl/xml/io_ext_mem_interface.xml
/socgen/trunk/projects/io/ip/io_gpio/rtl/xml/io_gpio.xml
/socgen/trunk/projects/io/ip/io_module/rtl/xml/io_module.xml
/socgen/trunk/projects/io/ip/io_module/rtl/xml/io_module_gpio.xml
/socgen/trunk/projects/io/ip/io_module/rtl/xml/io_module_mouse.xml
/socgen/trunk/projects/io/ip/io_module/sim/xml/io_module_default.xml
/socgen/trunk/projects/io/ip/io_module/sim/xml/io_module_mouse_mouse.xml
/socgen/trunk/projects/io/ip/io_pic/rtl/xml/io_pic.xml
/socgen/trunk/projects/io/ip/io_ps2/rtl/xml/io_ps2.xml
/socgen/trunk/projects/io/ip/io_ps2/sim/xml/io_ps2_default.xml
/socgen/trunk/projects/io/ip/io_timer/rtl/xml/io_timer.xml
/socgen/trunk/projects/io/ip/io_uart/rtl/xml/io_uart.xml
/socgen/trunk/projects/io/ip/io_utimer/rtl/xml/io_utimer.xml
/socgen/trunk/projects/io/ip/io_vga/rtl/xml/io_vga.xml
/socgen/trunk/projects/io/ip/io_vic/rtl/xml/io_vic.xml
/socgen/trunk/projects/logic/ip/disp_io/rtl/xml/disp_io.xml
/socgen/trunk/projects/logic/ip/disp_io/sim/xml/disp_io_default.xml
/socgen/trunk/projects/logic/ip/flash_memcontrl/rtl/verilog/top
/socgen/trunk/projects/logic/ip/flash_memcontrl/rtl/verilog/top.body
/socgen/trunk/projects/logic/ip/flash_memcontrl/rtl/xml/flash_memcontrl.xml
/socgen/trunk/projects/logic/ip/flash_memcontrl/sim/verilog/tb.ext
/socgen/trunk/projects/logic/ip/flash_memcontrl/sim/xml/flash_memcontrl_default.xml
/socgen/trunk/projects/logic/ip/micro_bus/rtl/xml/micro_bus.xml
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/xml/ps2_interface.xml
/socgen/trunk/projects/logic/ip/ps2_interface/sim/xml/ps2_interface_default.xml
/socgen/trunk/projects/logic/ip/ps2_interface/sim/xml/ps2_interface_mouse.xml
/socgen/trunk/projects/logic/ip/ps2_interface/soc/design.soc
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/verilog/top.body
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/verilog/top.body.fifo
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/xml/serial_rcvr.xml
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/xml/serial_rcvr_fifo.xml
/socgen/trunk/projects/logic/ip/serial_rcvr/sim/xml/serial_rcvr_default.xml
/socgen/trunk/projects/logic/ip/serial_rcvr/sim/xml/serial_rcvr_fifo_default.xml
/socgen/trunk/projects/logic/ip/uart/rtl/xml/uart.xml
/socgen/trunk/projects/logic/ip/uart/rtl/xml/uart_rx.xml
/socgen/trunk/projects/logic/ip/uart/rtl/xml/uart_rxtx.xml
/socgen/trunk/projects/logic/ip/uart/rtl/xml/uart_tx.xml
/socgen/trunk/projects/logic/ip/uart/sim/xml/uart_default.xml
/socgen/trunk/projects/logic/ip/uart/sim/xml/uart_divide.xml
/socgen/trunk/projects/logic/ip/uart/sim/xml/uart_rxtx_default.xml
/socgen/trunk/projects/logic/ip/uart/sim/xml/uart_rx_default.xml
/socgen/trunk/projects/logic/ip/usb_epp/rtl/xml/usb_epp.xml
/socgen/trunk/projects/logic/ip/usb_epp/sim/xml/usb_epp_default.xml
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl.xml
/socgen/trunk/projects/logic/ip/vga_char_ctrl/sim/xml/vga_char_ctrl_default.xml
/socgen/trunk/projects/logic/ip/vga_char_ctrl/sim/xml/vga_char_ctrl_default_600x432.xml
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502.xml
/socgen/trunk/projects/Mos6502/ip/T6502/sim/verilog/tb.ext_m
/socgen/trunk/projects/Mos6502/ip/T6502/sim/xml/T6502_inst_2_test.xml
/socgen/trunk/projects/Mos6502/ip/T6502/sim/xml/T6502_io_irq_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502/sim/xml/T6502_io_poll_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502/sim/xml/T6502_irq_2_test.xml
/socgen/trunk/projects/Mos6502/ip/T6502/sim/xml/T6502_kim_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502/sim/xml/T6502_tim_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/xml/T6502_cpu.xml
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/sim/xml/T6502_cpu_inst_2_test.xml
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/rtl/xml/T6502_cpu_alu_logic.xml
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/sim/xml/T6502_cpu_alu_logic_alu_logic_test.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/xml/mrisc_ind_mem.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/xml/mrisc_loop.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/xml/mrisc_rf1.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/xml/mrisc_rf2.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/xml/mrisc_rf3.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/xml/mrisc_sanity1.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/xml/mrisc_sanity2.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_ind_mem.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_loop.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_rf1.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_rf2.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_rf3.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_sanity1.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_sanity2.xml
/socgen/trunk/projects/pic_micro/ip/soc/rtl/xml/soc_mrisc_io.xml
/socgen/trunk/projects/pic_micro/ip/soc/sim/xml/soc_mrisc_io_mouse_mrisc.xml
/socgen/trunk/projects/targets
/socgen/trunk/projects/targets/bin
/socgen/trunk/projects/targets/ip
/socgen/trunk/projects/targets/ip/Basys
/socgen/trunk/projects/targets/ip/Basys/bsdl
/socgen/trunk/projects/targets/ip/Basys/bsdl/xc3s100e_tq144.bsd
/socgen/trunk/projects/targets/ip/Basys/bsdl/xcf02s_vo20.bsd
/socgen/trunk/projects/targets/ip/Basys/cclk.ut
/socgen/trunk/projects/targets/ip/Basys/jtag.ut
/socgen/trunk/projects/targets/ip/Basys/lib
/socgen/trunk/projects/targets/ip/Basys/lib/ip
/socgen/trunk/projects/targets/ip/Basys/lib/ip/cde_clock
/socgen/trunk/projects/targets/ip/Basys/lib/ip/cde_clock/rtl
/socgen/trunk/projects/targets/ip/Basys/lib/ip/cde_clock/rtl/verilog
/socgen/trunk/projects/targets/ip/Basys/lib/ip/cde_clock/rtl/verilog/syn
/socgen/trunk/projects/targets/ip/Basys/lib/ip/cde_clock/rtl/verilog/syn/cde_clock_sys.v
/socgen/trunk/projects/targets/ip/Basys/lib/ip/cde_jtag
/socgen/trunk/projects/targets/ip/Basys/lib/ip/cde_jtag/rtl
/socgen/trunk/projects/targets/ip/Basys/lib/ip/cde_jtag/rtl/gen
/socgen/trunk/projects/targets/ip/Basys/lib/ip/cde_jtag/rtl/gen/syn
/socgen/trunk/projects/targets/ip/Basys/lib/ip/cde_jtag/rtl/gen/syn/cde_jtag.v
/socgen/trunk/projects/targets/ip/Basys/Makefile.brd
/socgen/trunk/projects/targets/ip/Basys/Pad_Ring.ucf
/socgen/trunk/projects/targets/ip/Basys/soc
/socgen/trunk/projects/targets/ip/Basys/soc/design.soc
/socgen/trunk/projects/targets/ip/Nexys
/socgen/trunk/projects/targets/ip/Nexys/bsdl
/socgen/trunk/projects/targets/ip/Nexys/bsdl/xc3s1000l_fg456_1532.bsd
/socgen/trunk/projects/targets/ip/Nexys/bsdl/xcf04s_vo20.bsd
/socgen/trunk/projects/targets/ip/Nexys/cclk.ut
/socgen/trunk/projects/targets/ip/Nexys/jtag.ut
/socgen/trunk/projects/targets/ip/Nexys/lib
/socgen/trunk/projects/targets/ip/Nexys/lib/ip
/socgen/trunk/projects/targets/ip/Nexys/lib/ip/cde_clock
/socgen/trunk/projects/targets/ip/Nexys/lib/ip/cde_clock/rtl
/socgen/trunk/projects/targets/ip/Nexys/lib/ip/cde_clock/rtl/verilog
/socgen/trunk/projects/targets/ip/Nexys/lib/ip/cde_clock/rtl/verilog/syn
/socgen/trunk/projects/targets/ip/Nexys/lib/ip/cde_clock/rtl/verilog/syn/cde_clock_sys.v
/socgen/trunk/projects/targets/ip/Nexys/lib/ip/cde_jtag
/socgen/trunk/projects/targets/ip/Nexys/lib/ip/cde_jtag/rtl
/socgen/trunk/projects/targets/ip/Nexys/lib/ip/cde_jtag/rtl/gen
/socgen/trunk/projects/targets/ip/Nexys/lib/ip/cde_jtag/rtl/gen/syn
/socgen/trunk/projects/targets/ip/Nexys/lib/ip/cde_jtag/rtl/gen/syn/cde_jtag.v
/socgen/trunk/projects/targets/ip/Nexys/Makefile.brd
/socgen/trunk/projects/targets/ip/Nexys/Pad_Ring.ucf
/socgen/trunk/projects/targets/ip/Nexys/soc
/socgen/trunk/projects/targets/ip/Nexys/soc/design.soc
/socgen/trunk/projects/targets/ip/Nexys2
/socgen/trunk/projects/targets/ip/Nexys2/bsdl
/socgen/trunk/projects/targets/ip/Nexys2/bsdl/xc3s1200e_fg320_1532.bsd
/socgen/trunk/projects/targets/ip/Nexys2/bsdl/xcf04s_vo20.bsd
/socgen/trunk/projects/targets/ip/Nexys2/cclk.ut
/socgen/trunk/projects/targets/ip/Nexys2/jtag.ut
/socgen/trunk/projects/targets/ip/Nexys2/lib
/socgen/trunk/projects/targets/ip/Nexys2/lib/ip
/socgen/trunk/projects/targets/ip/Nexys2/lib/ip/cde_clock
/socgen/trunk/projects/targets/ip/Nexys2/lib/ip/cde_clock/rtl
/socgen/trunk/projects/targets/ip/Nexys2/lib/ip/cde_clock/rtl/verilog
/socgen/trunk/projects/targets/ip/Nexys2/lib/ip/cde_clock/rtl/verilog/syn
/socgen/trunk/projects/targets/ip/Nexys2/lib/ip/cde_clock/rtl/verilog/syn/cde_clock_sys.v
/socgen/trunk/projects/targets/ip/Nexys2/lib/ip/cde_jtag
/socgen/trunk/projects/targets/ip/Nexys2/lib/ip/cde_jtag/rtl
/socgen/trunk/projects/targets/ip/Nexys2/lib/ip/cde_jtag/rtl/gen
/socgen/trunk/projects/targets/ip/Nexys2/lib/ip/cde_jtag/rtl/gen/syn
/socgen/trunk/projects/targets/ip/Nexys2/lib/ip/cde_jtag/rtl/gen/syn/cde_jtag.v
/socgen/trunk/projects/targets/ip/Nexys2/Makefile.brd
/socgen/trunk/projects/targets/ip/Nexys2/Pad_Ring.ucf
/socgen/trunk/projects/targets/ip/Nexys2/soc
/socgen/trunk/projects/targets/ip/Nexys2/soc/design.soc
/socgen/trunk/projects/Testbench/ip/clock_gen/rtl/xml/clock_gen.xml
/socgen/trunk/projects/Testbench/ip/gpio_model/rtl/xml/gpio_model.xml
/socgen/trunk/projects/Testbench/ip/io_probe/rtl/xml/io_probe.xml
/socgen/trunk/projects/Testbench/ip/jtag_model/rtl/xml/jtag_model.xml
/socgen/trunk/projects/Testbench/ip/micro_bus16_model/rtl/xml/micro_bus16_model.xml
/socgen/trunk/projects/Testbench/ip/micro_bus_model/rtl/xml/micro_bus_model.xml
/socgen/trunk/projects/Testbench/ip/mt45w8mw12/rtl/xml/mt45w8mw12.xml
/socgen/trunk/projects/Testbench/ip/ps2_host/rtl/xml/ps2_host.xml
/socgen/trunk/projects/Testbench/ip/ps2_model/rtl/xml/ps2_model.xml
/socgen/trunk/projects/Testbench/ip/template/rtl/xml/xxx.xml
/socgen/trunk/projects/Testbench/ip/uart_host/rtl/xml/uart_host.xml
/socgen/trunk/projects/Testbench/ip/uart_model/rtl/xml/uart_model.xml
/socgen/trunk/tools/sys/build_sim_filelists
/socgen/trunk/tools/sys/build_verilog
/socgen/trunk/tools/sys/build_verilogLibraryFile
/socgen/trunk/tools/sys/soc_builder
/socgen/trunk/tools/sys/soc_generate
/socgen/trunk/tools/sys/workspace

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