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[/] [socgen/] [trunk/] [tools/] [verilog/] - Rev 120

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Last modification

  • Rev 120, 2012-10-22 20:40:55 GMT
  • Author: jt_eaton
  • Log message:
    clean up componentGenerators names and directories
    sim + lint now synthesis TestBench
Path
/socgen/trunk/doc/src/drawing/sch/Busdef_guide_1.sch
/socgen/trunk/doc/src/drawing/sch/Busdef_guide_2.sch
/socgen/trunk/doc/src/drawing/sch/Busdef_guide_3.sch
/socgen/trunk/doc/src/drawing/sch/cde_pad_in_dig.sch
/socgen/trunk/doc/src/drawing/sch/cde_pad_od_dig.sch
/socgen/trunk/doc/src/drawing/sch/cde_pad_out_dig.sch
/socgen/trunk/doc/src/drawing/sch/cde_pad_se_dig.sch
/socgen/trunk/doc/src/drawing/sch/cde_pad_tri_dig.sch
/socgen/trunk/doc/src/drawing/sch/fund_reset_fig1.sch
/socgen/trunk/doc/src/drawing/sch/fund_reset_fig2.sch
/socgen/trunk/doc/src/drawing/sch/fund_reset_fig3.sch
/socgen/trunk/doc/src/drawing/sch/fund_reset_fig4.sch
/socgen/trunk/doc/src/drawing/sch/fund_reset_fig5.sch
/socgen/trunk/doc/src/drawing/sch/fund_reset_fig6.sch
/socgen/trunk/doc/src/drawing/sch/um-100_cde_clock_sys_sym.sch
/socgen/trunk/doc/src/drawing/sch/um-100_cde_jtag_def_sym.sch
/socgen/trunk/doc/src/drawing/sch/um-100_cde_sram_be_sym.sch
/socgen/trunk/doc/src/drawing/sch/um-100_cde_sram_def_sym.sch
/socgen/trunk/doc/src/drawing/sch/um-100_cde_sram_dp_sym.sch
/socgen/trunk/doc/src/drawing/sch/um-150_cde_jtag_rpc_sym.sch
/socgen/trunk/doc/src/drawing/sch/um-150_cde_reset_sym.sch
/socgen/trunk/doc/src/drawing/sch/um-150_cde_sync_sym.sch
/socgen/trunk/doc/src/drawing/sym/cde_clock_diff_testmux.sym
/socgen/trunk/doc/src/drawing/sym/cde_clock_gater.sym
/socgen/trunk/doc/src/drawing/sym/cde_clock_multiplier.sym
/socgen/trunk/doc/src/drawing/sym/cde_clock_sys.sym
/socgen/trunk/doc/src/drawing/sym/cde_clock_testmux.sym
/socgen/trunk/doc/src/drawing/sym/cde_divider_def.sym
/socgen/trunk/doc/src/drawing/sym/cde_fifo_def.sym
/socgen/trunk/doc/src/drawing/sym/cde_jtag_classic_rpc_in_reg.sym
/socgen/trunk/doc/src/drawing/sym/cde_jtag_classic_rpc_reg.sym
/socgen/trunk/doc/src/drawing/sym/cde_jtag_def.sym
/socgen/trunk/doc/src/drawing/sym/cde_jtag_rpc_in_reg.sym
/socgen/trunk/doc/src/drawing/sym/cde_jtag_rpc_reg.sym
/socgen/trunk/doc/src/drawing/sym/cde_lifo_def.sym
/socgen/trunk/doc/src/drawing/sym/cde_mult_generic.sym
/socgen/trunk/doc/src/drawing/sym/cde_mult_ord_r4.sym
/socgen/trunk/doc/src/drawing/sym/cde_mult_serial.sym
/socgen/trunk/doc/src/drawing/sym/cde_pad_in_dig.sym
/socgen/trunk/doc/src/drawing/sym/cde_pad_od_dig.sym
/socgen/trunk/doc/src/drawing/sym/cde_pad_out_dig.sym
/socgen/trunk/doc/src/drawing/sym/cde_pad_se_dig.sym
/socgen/trunk/doc/src/drawing/sym/cde_pad_tri_dig.sym
/socgen/trunk/doc/src/drawing/sym/cde_prescale_def.sym
/socgen/trunk/doc/src/drawing/sym/cde_reset_asyncdisable.sym
/socgen/trunk/doc/src/drawing/sym/cde_reset_def.sym
/socgen/trunk/doc/src/drawing/sym/cde_serial_rcvr.sym
/socgen/trunk/doc/src/drawing/sym/cde_serial_xmit.sym
/socgen/trunk/doc/src/drawing/sym/cde_sram_be.sym
/socgen/trunk/doc/src/drawing/sym/cde_sram_def.sym
/socgen/trunk/doc/src/drawing/sym/cde_sram_dp.sym
/socgen/trunk/doc/src/drawing/sym/cde_sync_def.sym
/socgen/trunk/doc/src/drawing/sym/cde_sync_with_hysteresis.sym
/socgen/trunk/doc/src/drawing/sym/cde_sync_with_reset.sym
/socgen/trunk/doc/src/drawing/sym/io_pad.sym
/socgen/trunk/doc/src/png/cde_pad_in_dig.png
/socgen/trunk/doc/src/png/cde_pad_od_dig.png
/socgen/trunk/doc/src/png/cde_pad_out_dig.png
/socgen/trunk/doc/src/png/cde_pad_tri_dig.png
/socgen/trunk/doc/src/png/um-100_cde_clock_sys_sym.png
/socgen/trunk/doc/src/png/um-100_cde_jtag_def_sym.png
/socgen/trunk/doc/src/png/um-100_cde_pad_se_dig.png
/socgen/trunk/doc/src/png/um-100_cde_sram_be_sym.png
/socgen/trunk/doc/src/png/um-100_cde_sram_def_sym.png
/socgen/trunk/doc/src/png/um-100_cde_sram_dp_sym.png
/socgen/trunk/doc/src/png/um-150_cde_jtag_rpc_sym.png
/socgen/trunk/doc/src/png/um-150_cde_reset_sym.png
/socgen/trunk/doc/src/png/um-150_cde_sync_sym.png
/socgen/trunk/projects/accellera.org
/socgen/trunk/projects/accellera.org/ieee1149.1
/socgen/trunk/projects/accellera.org/ieee1149.1/JTAG_EXT
/socgen/trunk/projects/accellera.org/ieee1149.1/JTAG_EXT/2001-1.0
/socgen/trunk/projects/accellera.org/ieee1149.1/JTAG_EXT/2001-1.0/xml
/socgen/trunk/projects/accellera.org/ieee1149.1/JTAG_EXT/2001-1.0/xml/JTAG_EXT.xml
/socgen/trunk/projects/accellera.org/ieee1149.1/JTAG_EXT/2001-1.0/xml/JTAG_EXT_rtl.xml
/socgen/trunk/projects/accellera.org/ieee1149.1/JTAG_INT
/socgen/trunk/projects/accellera.org/ieee1149.1/JTAG_INT/2001-1.0
/socgen/trunk/projects/accellera.org/ieee1149.1/JTAG_INT/2001-1.0/xml
/socgen/trunk/projects/accellera.org/ieee1149.1/JTAG_INT/2001-1.0/xml/JTAG_INT.xml
/socgen/trunk/projects/accellera.org/ieee1149.1/JTAG_INT/2001-1.0/xml/JTAG_INT_rtl.xml
/socgen/trunk/projects/accellera.org/interrupt
/socgen/trunk/projects/accellera.org/interrupt/INTERRUPT_IP
/socgen/trunk/projects/accellera.org/interrupt/INTERRUPT_IP/1.0
/socgen/trunk/projects/accellera.org/interrupt/INTERRUPT_IP/1.0/xml
/socgen/trunk/projects/accellera.org/interrupt/INTERRUPT_IP/1.0/xml/INTERRUPT_IP.xml
/socgen/trunk/projects/accellera.org/interrupt/INTERRUPT_IP/1.0/xml/INTERRUPT_IP_rtl.xml
/socgen/trunk/projects/accellera.org/interrupt/INTERRUPT_IP_N
/socgen/trunk/projects/accellera.org/interrupt/INTERRUPT_IP_N/1.0
/socgen/trunk/projects/accellera.org/interrupt/INTERRUPT_IP_N/1.0/xml
/socgen/trunk/projects/accellera.org/interrupt/INTERRUPT_IP_N/1.0/xml/INTERRUPT_IP_N.xml
/socgen/trunk/projects/accellera.org/interrupt/INTERRUPT_IP_N/1.0/xml/INTERRUPT_IP_N_rtl.xml
/socgen/trunk/projects/accellera.org/interrupt/INTERRUPT_PROCESSOR
/socgen/trunk/projects/accellera.org/interrupt/INTERRUPT_PROCESSOR/1.0
/socgen/trunk/projects/accellera.org/interrupt/INTERRUPT_PROCESSOR/1.0/xml
/socgen/trunk/projects/accellera.org/interrupt/INTERRUPT_PROCESSOR/1.0/xml/INTERRUPT_PROCESSOR.xml
/socgen/trunk/projects/accellera.org/interrupt/INTERRUPT_PROCESSOR/1.0/xml/INTERRUPT_PROCESSOR_rtl.xml
/socgen/trunk/projects/accellera.org/interrupt/INTERRUPT_PROCESSOR_N
/socgen/trunk/projects/accellera.org/interrupt/INTERRUPT_PROCESSOR_N/1.0
/socgen/trunk/projects/accellera.org/interrupt/INTERRUPT_PROCESSOR_N/1.0/xml
/socgen/trunk/projects/accellera.org/interrupt/INTERRUPT_PROCESSOR_N/1.0/xml/INTERRUPT_PROCESSOR_N.xml
/socgen/trunk/projects/accellera.org/interrupt/INTERRUPT_PROCESSOR_N/1.0/xml/INTERRUPT_PROCESSOR_N_rtl.xml
/socgen/trunk/projects/opencores.org/Basys/ip-xact
/socgen/trunk/projects/opencores.org/Basys/ip-xact/library.xml
/socgen/trunk/projects/opencores.org/Basys/ip/cde_clock/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Basys/ip/cde_clock/rtl/verilog/syn/cde_clock_sys.v
/socgen/trunk/projects/opencores.org/Basys/ip/cde_clock/rtl/xml/cde_clock_sys.xml
/socgen/trunk/projects/opencores.org/Basys/ip/cde_jtag/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Basys/ip/cde_jtag/rtl/verilog
/socgen/trunk/projects/opencores.org/Basys/ip/cde_jtag/rtl/verilog/syn
/socgen/trunk/projects/opencores.org/Basys/ip/cde_jtag/rtl/verilog/syn/cde_jtag_def.v
/socgen/trunk/projects/opencores.org/Basys/ip/cde_jtag/rtl/views
/socgen/trunk/projects/opencores.org/Basys/ip/cde_jtag/rtl/xml/cde_jtag_def.xml
/socgen/trunk/projects/opencores.org/Basys/ip/fpga/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Basys/ip/fpga/rtl/xml/Basys_fpga_jtag_padring.xml
/socgen/trunk/projects/opencores.org/Basys/ip/fpga/rtl/xml/Basys_fpga_padring.xml
/socgen/trunk/projects/opencores.org/Busdefs/soc
/socgen/trunk/projects/opencores.org/cde/doc/drawing/sym/cde_clock_sys.sym
/socgen/trunk/projects/opencores.org/cde/ip-xact
/socgen/trunk/projects/opencores.org/cde/ip-xact/library.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/verilog/cde_clock_sys
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/verilog/sim/cde_clock_sys.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/verilog/syn/cde_clock_sys.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_diff_testmux.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_dll.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_gater.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_sys.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_testmux.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/rtl/xml/cde_divider_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/rtl/xml/cde_fifo_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/verilog/cde_jtag_classic_rpc_in_reg.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/verilog/cde_jtag_classic_rpc_reg.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/verilog/cde_jtag_rpc_in_reg.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/verilog/cde_jtag_rpc_reg.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/views
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_in_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_rpc_in_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_rpc_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/icarus/default/test_define
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/xml/cde_jtag_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/rtl/xml/cde_lifo_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_generic.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_ord_r4.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_serial.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_generic_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_ord_r4_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_serial_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/verilog/sim/cde_pad_diff_dig.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/verilog/sim/cde_pad_tri_dig.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/verilog/syn/cde_pad_diff_dig.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/verilog/syn/cde_pad_tri_dig.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_diff_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_in_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_od_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_out_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_se_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_tri_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/rtl/xml/cde_prescale_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/xml/cde_reset_asyncdisable.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/xml/cde_reset_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/rtl/xml/cde_serial_rcvr.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/rtl/xml/cde_serial_xmit.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_be.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_dp.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/xml/cde_sync_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/xml/cde_sync_with_hysteresis.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/xml/cde_sync_with_reset.xml
/socgen/trunk/projects/opencores.org/fpgas/ip-xact
/socgen/trunk/projects/opencores.org/fpgas/ip-xact/library.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_def.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_default.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_irq_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_poll_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_irq_2_test.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_kim_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_tim_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/xml/Nexys2_T6502_tb.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/soc
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip-xact
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip-xact/library.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/xml/Basys_mrisc_def.design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/xml/Basys_mrisc_def.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/xml/Basys_mrisc_default.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/xml/Basys_mrisc_loop.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/sim/xml/Basys_mrisc_tb.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/soc
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/rtl/xml/Basys_soc_mrisc_io_mouse.design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/rtl/xml/Basys_soc_mrisc_io_mouse.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/rtl/xml/Basys_soc_mrisc_io_mouse_default.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/rtl/xml/Basys_soc_mrisc_io_mouse_mouse.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/sim/xml/Basys_soc_mrisc_io_mouse_tb.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/soc
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse_default.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse_mouse.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/sim/xml/Nexys2_soc_mrisc_io_mouse_tb.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/soc
/socgen/trunk/projects/opencores.org/fpga_or1200/ip-xact
/socgen/trunk/projects/opencores.org/fpga_or1200/ip-xact/library.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_def.design.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_def.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_default.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_fpga.design.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_uart.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/xml/Nexys2_minsoc_tb.design.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/xml/Nexys2_minsoc_tb.xml
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