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Subversion Repositories adv_debug_sys

[/] - Rev 42

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Last modification

  • Rev 42, 2010-03-31 18:36:20 GMT
  • Author: nyawn
  • Log message:
    Added (experimental) Actel UJTAG TAP core. Added JTAG serial port feature to debug hardware core and JTAG bridge program. Added more speedups for USB JTAG cables to bridge program - USB-Blaster users should now see ~30k/sec upload speeds. Updated documentation.
Path
/adv_debug_sys/trunk/Doc/or1k_debug_sys_manual.pdf
/adv_debug_sys/trunk/Doc/src/or1k_debug_sys_manual.odt
/adv_debug_sys/trunk/Hardware/actel_ujtag
/adv_debug_sys/trunk/Hardware/actel_ujtag/doc
/adv_debug_sys/trunk/Hardware/actel_ujtag/doc/actel_ujtag.pdf
/adv_debug_sys/trunk/Hardware/actel_ujtag/doc/gpl-2.0.txt
/adv_debug_sys/trunk/Hardware/actel_ujtag/doc/License_FDL-1.2.txt
/adv_debug_sys/trunk/Hardware/actel_ujtag/doc/src
/adv_debug_sys/trunk/Hardware/actel_ujtag/doc/src/actel_ujtag.odt
/adv_debug_sys/trunk/Hardware/actel_ujtag/rtl
/adv_debug_sys/trunk/Hardware/actel_ujtag/rtl/verilog
/adv_debug_sys/trunk/Hardware/actel_ujtag/rtl/verilog/actel_ujtag.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/bench/jtag_serial_port
/adv_debug_sys/trunk/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/bench/jtag_serial_port/wave.do
/adv_debug_sys/trunk/Hardware/adv_dbg_if/bench/README_testbench.txt
/adv_debug_sys/trunk/Hardware/adv_dbg_if/doc/AdvancedDebugInterface.pdf
/adv_debug_sys/trunk/Hardware/adv_dbg_if/doc/src/AdvancedDebugInterface.odt
/adv_debug_sys/trunk/Hardware/adv_dbg_if/doc/src/jsp_submodule.odg
/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/adbg_jsp_biu.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/adbg_jsp_module.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/bytefifo.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/syncflop.v
/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl/verilog/syncreg.v
/adv_debug_sys/trunk/Software/adv_jtag_bridge/adv_dbg_commands.c
/adv_debug_sys/trunk/Software/adv_jtag_bridge/adv_dbg_commands.h
/adv_debug_sys/trunk/Software/adv_jtag_bridge/adv_jtag_bridge.c
/adv_debug_sys/trunk/Software/adv_jtag_bridge/dbg_api.c
/adv_debug_sys/trunk/Software/adv_jtag_bridge/dbg_api.h
/adv_debug_sys/trunk/Software/adv_jtag_bridge/doc/adv_jtag_bridge.pdf
/adv_debug_sys/trunk/Software/adv_jtag_bridge/doc/src/adv_jtag_bridge.odt
/adv_debug_sys/trunk/Software/adv_jtag_bridge/doc/src/ajb_block_diagram.odg
/adv_debug_sys/trunk/Software/adv_jtag_bridge/hardware_monitor.c
/adv_debug_sys/trunk/Software/adv_jtag_bridge/hardware_monitor.h
/adv_debug_sys/trunk/Software/adv_jtag_bridge/jsp_server.c
/adv_debug_sys/trunk/Software/adv_jtag_bridge/jsp_server.h
/adv_debug_sys/trunk/Software/adv_jtag_bridge/Makefile
/adv_debug_sys/trunk/Software/adv_jtag_bridge/README
/adv_debug_sys/trunk/Software/adv_jtag_bridge/rsp-server.c

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