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[/] [pulse_processing_algorithm/] - Rev 2

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Last modification

  • Rev 2, 2011-09-21 07:27:12 GMT
  • Author: panda_emc
  • Log message:
    This is a stable version, which works at maximum speed of 50 MHz
Path
/pulse_processing_algorithm/adc_flowcontrol.vhd
/pulse_processing_algorithm/async_fifo_16x65.xco
/pulse_processing_algorithm/baseline_follower.vhd
/pulse_processing_algorithm/blk_asy_fifo_511x32.edn
/pulse_processing_algorithm/blk_asy_fifo_511x32.xco
/pulse_processing_algorithm/blk_asy_fifo_1023x16.edn
/pulse_processing_algorithm/blk_asy_fifo_1023x16.xco
/pulse_processing_algorithm/block_ram.vhd
/pulse_processing_algorithm/CF_process.vhd
/pulse_processing_algorithm/CF_zeroX.vhd
/pulse_processing_algorithm/compare_a2b.vhd
/pulse_processing_algorithm/controller_ddr2_iobs.vhd
/pulse_processing_algorithm/control_feedback.vhd
/pulse_processing_algorithm/datapath_ddr2_iobs.vhd
/pulse_processing_algorithm/data_path_rst.vhd
/pulse_processing_algorithm/data_read.vhd
/pulse_processing_algorithm/data_read_controller.vhd
/pulse_processing_algorithm/data_write.vhd
/pulse_processing_algorithm/ddr2_data_path.vhd
/pulse_processing_algorithm/ddr2_dm.vhd
/pulse_processing_algorithm/ddr2_iobs.vhd
/pulse_processing_algorithm/ddr_address_generator.vhd
/pulse_processing_algorithm/ddr_clk_dcm.vhd
/pulse_processing_algorithm/dff_re.vhd
/pulse_processing_algorithm/event_detector.vhd
/pulse_processing_algorithm/FeatureExtraction.vhd
/pulse_processing_algorithm/fifo_0_wr_en.vhd
/pulse_processing_algorithm/fifo_1_wr_en.vhd
/pulse_processing_algorithm/flex_ram.vhd
/pulse_processing_algorithm/gate_generator.vhd
/pulse_processing_algorithm/history_max.vhd
/pulse_processing_algorithm/LICENSE
/pulse_processing_algorithm/moving_average_programmable.vhd
/pulse_processing_algorithm/mux_sre.vhd
/pulse_processing_algorithm/MWD_CF_process.vhd
/pulse_processing_algorithm/MWD_programmable.vhd
/pulse_processing_algorithm/mybufg.vhd
/pulse_processing_algorithm/output_mux.vhd
/pulse_processing_algorithm/output_select.vhd
/pulse_processing_algorithm/pipeline.vhd
/pulse_processing_algorithm/progdelay_pipeline.vhd
/pulse_processing_algorithm/rd_gray_cntr.vhd
/pulse_processing_algorithm/READ_ME
/pulse_processing_algorithm/ringbuffer_feed.vhd
/pulse_processing_algorithm/s3_ddr_iob.vhd
/pulse_processing_algorithm/s3_dqs_iob.vhd
/pulse_processing_algorithm/sample_counter.vhd
/pulse_processing_algorithm/shaper.vhd
/pulse_processing_algorithm/sis3302_macros_updated
/pulse_processing_algorithm/sis3302_macros_updated/controller.ngc
/pulse_processing_algorithm/sis3302_macros_updated/ddr2_readwrite_fsm.ngc
/pulse_processing_algorithm/sis3302_macros_updated/gamma_adc_sample_logic.ngc
/pulse_processing_algorithm/sis3302_macros_updated/infrastructure.ngc
/pulse_processing_algorithm/sis3302_macros_updated/ram_address_fifo_pipe.ngc
/pulse_processing_algorithm/sis3302_macros_updated/ram_block_256_16.ngo
/pulse_processing_algorithm/sis3302_macros_updated/th_comp_17bits.ngo
/pulse_processing_algorithm/sis3302_macros_updated/th_comp_17bits_c_compare_v9_0_xst_1.ngc
/pulse_processing_algorithm/sis3302_macros_updated/vme_intf.ngc
/pulse_processing_algorithm/sis3302_macros_updated/vme_mca_ram_read_controller.ngc
/pulse_processing_algorithm/sis3302_macros_updated/vme_ram_test_write_controller.ngc
/pulse_processing_algorithm/SISO_add_a.vhd
/pulse_processing_algorithm/SISO_sub_a.vhd
/pulse_processing_algorithm/Struck_FE_GPL.ise
/pulse_processing_algorithm/Struck_MWD_CF_registers.doc
/pulse_processing_algorithm/successive_interp.vhd
/pulse_processing_algorithm/sys_clk_dcm.vhd
/pulse_processing_algorithm/timing_linear_interp.vhd
/pulse_processing_algorithm/top.ucf
/pulse_processing_algorithm/top.vhd
/pulse_processing_algorithm/window_diff.vhd
/pulse_processing_algorithm/window_subtractor_programmable.vhd
/pulse_processing_algorithm/wr_gray_cntr.vhd

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