URL https://opencores.org/ocsvn/reed_solomon_decoder/reed_solomon_decoder/trunk

Subversion Repositories reed_solomon_decoder

[/] [reed_solomon_decoder/] - Rev 2

Rev 2, 2009-07-06 09:59:18 GMT
Author: aelmahmoudy
Log message:
Initial commit of Reed Solomon Decoder Verilog core (204,188,8)
corrects up to 8 errors per block
Pipelined and verfied on FPGA

Path
/reed_solomon_decoder/trunk/document
/reed_solomon_decoder/trunk/document/Reed_Solomon_Decoder_204_188.pdf
/reed_solomon_decoder/trunk/rtl
/reed_solomon_decoder/trunk/rtl/BM_lamda.v
/reed_solomon_decoder/trunk/rtl/DP_RAM.v
/reed_solomon_decoder/trunk/rtl/error_correction.v
/reed_solomon_decoder/trunk/rtl/GF_matrix_ascending_binary.v
/reed_solomon_decoder/trunk/rtl/GF_matrix_dec.v
/reed_solomon_decoder/trunk/rtl/GF_mult_add_syndromes.v
/reed_solomon_decoder/trunk/rtl/input_syndromes.v
/reed_solomon_decoder/trunk/rtl/lamda_roots.v
/reed_solomon_decoder/trunk/rtl/Omega_Phy.v
/reed_solomon_decoder/trunk/rtl/out_stage.v
/reed_solomon_decoder/trunk/rtl/RS_dec.v
/reed_solomon_decoder/trunk/rtl/transport_in2out.v
/reed_solomon_decoder/trunk/simulation
/reed_solomon_decoder/trunk/simulation/do.do
/reed_solomon_decoder/trunk/simulation/input_RS_blocks
/reed_solomon_decoder/trunk/simulation/output_RS_blocks
/reed_solomon_decoder/trunk/simulation/RS_dec_tb.v
/reed_solomon_decoder/trunk/simulation/RS_test_vectors.m
/reed_solomon_decoder/trunk/simulation/wave.do