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[/] [socgen/] - Rev 116

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Last modification

  • Rev 116, 2012-06-12 01:01:04 GMT
  • Author: jt_eaton
  • Log message:
    added build_header
    now use build_register for all spr components
    resynced or1200 code back to use orbuild toolchain
Path
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/ip-xact/cde_sram_def.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/ip-xact/cde_sram_dp.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/sim/cde_sram_be.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/syn/cde_sram_be.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_be.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_def.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_dp.design.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_core.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_default.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_irq_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_poll_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_irq_2_test.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_kim_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_tim_2.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/icarus/uart-nocache_emb/wave.sav
/socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/rtl/xml/io_ext_mem_interface_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/sim/xml/io_ext_mem_interface_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_gpio/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/io/ip/io_gpio/rtl/xml/io_gpio_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_gpio/sim/xml/io_gpio_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_gpio.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_mouse.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_gpio_tb.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_gpio_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_mouse_tb.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_mouse_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_tb.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_pic/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/io/ip/io_pic/rtl/xml/io_pic_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_pic/sim/xml/io_pic_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/rtl/xml/io_ps2_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/rtl/xml/io_ps2_mouse.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/icarus/default/test_define
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/icarus/mouse_default/test_define
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/verilog/tb.ext
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/xml/io_ps2_mouse_tb.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/xml/io_ps2_mouse_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/xml/io_ps2_tb.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/xml/io_ps2_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_timer/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/io/ip/io_timer/rtl/xml/io_timer_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_timer/sim/xml/io_timer_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_rx.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_rxtx.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_tx.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_rxtx_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_rx_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_tx_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_utimer/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/io/ip/io_utimer/rtl/xml/io_utimer_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_utimer/sim/xml/io_utimer_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vga/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/io/ip/io_vga/rtl/xml/io_vga_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vga/sim/xml/io_vga_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vic/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/io/ip/io_vic/rtl/xml/io_vic_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vic/sim/xml/io_vic_tb.xml
/socgen/trunk/projects/opencores.org/or1k/bin/compile
/socgen/trunk/projects/opencores.org/or1k/bin/Makefile.or32
/socgen/trunk/projects/opencores.org/or1k/doc/pdf/journal.pdf
/socgen/trunk/projects/opencores.org/or1k/doc/src/journal.html
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/ip-xact/or1200_null.designCfg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/or1200_monitor.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/or1200_monitor_defines.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/top.or1200_mon
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_clkgen.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_dbg.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_dbg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_null.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-basic/wave.sav
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-dsx
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-dsx/dmp_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-dsx/test_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-dsx/wave.sav
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-dsxinsn
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-dsxinsn/dmp_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-dsxinsn/test_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-dsxinsn/wave.sav
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-float/wave.sav
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-fp/test_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-fp/wave.sav
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-mac/wave.sav
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-maci/wave.sav
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-no_code_sprs_sys/test_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-no_code_sprs_sys/wave.sav
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-tick/wave.sav
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200_q-basic
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200_q-basic/dmp_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200_q-basic/test_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200_q-basic/wave.sav
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/xml/or1200_dbg_tb.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/xml/or1200_dbg_tb.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/or1200_dc_fsm.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/or1200_ic_fsm.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/top.data
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml/or1200_cache_data.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml/or1200_cache_inst.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cache_en
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_cfgr
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_except
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_genpc
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_lsu
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_rf
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_sprs
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_spr_mux
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_alu.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_boot.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_cfgr.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_ctrl.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_dbg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_def.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_du.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_except.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_freeze.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_genpc.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_if.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_lsu.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_operandmuxes.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_rf.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_sprs.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_spr_mux.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_wbmux.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_fpu/rtl/verilog/top.def
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_fpu/rtl/xml/or1200_fpu_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/or1200_dmmu_tlb.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/or1200_immu_tlb.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/top.data
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/top.inst
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml/or1200_mmu_data.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml/or1200_mmu_inst.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/rtl/verilog/top.def
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/rtl/xml/or1200_mult_mac_asic.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/rtl/xml/or1200_mult_mac_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/rtl/verilog/top
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/rtl/verilog/top.def
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/rtl/xml/or1200_pic_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/rtl/verilog/top
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/rtl/verilog/top.def
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/rtl/xml/or1200_pm_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/verilog/defines
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/verilog/or1200_spram_2048x32.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/verilog/top.def
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/verilog/top.split
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/xml/or1200_qmem_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/xml/or1200_qmem_split.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/rtl/xml/or1200_sb_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/rtl/verilog/top
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/rtl/verilog/top.def
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/rtl/xml/or1200_tt_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/xml/or1200_wb_biu_def.xml
/socgen/trunk/projects/opencores.org/or1k/sw/backend/link.ld
/socgen/trunk/projects/opencores.org/or1k/sw/cache/cache.S
/socgen/trunk/projects/opencores.org/or1k/sw/crt0/crt0.S
/socgen/trunk/projects/opencores.org/or1k/sw/intgen-intsyscall/intgen-intsyscall.S
/socgen/trunk/projects/opencores.org/or1k/sw/intgen-ticksyscall/intgen-ticksyscall.S
/socgen/trunk/projects/opencores.org/or1k/sw/mmu/mmu.S
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-basic/or1200-basic.S
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-cy/or1200-cy.S
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-dctest/Makefile
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-div/Makefile
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-dsx
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-dsx/Makefile
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-dsx/or1200-dsx.S
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-dsxinsn
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-dsxinsn/Makefile
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-dsxinsn/or1200-dsxinsn.S
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-except/or1200-except.S
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-ext/or1200-ext.S
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-ffl1/or1200-ffl1.S
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-float/Makefile
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-fp/or1200-fp.S
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-mac/or1200-mac.S
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-maci/or1200-maci.S
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-mmu/Makefile
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-mul/Makefile
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-ov/or1200-ov.S
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-pm/or1200-pm.S
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-qmem/or1200-qmem.S
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-rfe/or1200-rfe.S
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-rfemmu/or1200-rfemmu.S
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-sb/or1200-sb.S
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-simple/Makefile
/socgen/trunk/projects/opencores.org/or1k/sw/or1200-tick/or1200-tick.S
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-basic
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-cbasic
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-cy
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-dctest
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-except
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-ext
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-ffl1
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-float
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-fp
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-intsyscall
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-linkregtest
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-mac
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-maci
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-mmu
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-ov
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-rfe
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-rfemmu
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-sf
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-simple
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