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Last modification

  • Rev 122, 2012-11-30 02:48:43 GMT
  • Author: jt_eaton
  • Log message:
    Moved Nexys2 from opencores.org to digilentinc.com
    Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components
Path
/socgen/trunk/projects/digilentinc.com
/socgen/trunk/projects/digilentinc.com/Nexys2
/socgen/trunk/projects/digilentinc.com/Nexys2/bin
/socgen/trunk/projects/digilentinc.com/Nexys2/bin/repeater
/socgen/trunk/projects/digilentinc.com/Nexys2/ip
/socgen/trunk/projects/digilentinc.com/Nexys2/ip-xact
/socgen/trunk/projects/digilentinc.com/Nexys2/ip-xact/library.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_clock
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_clock/bin
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_clock/bin/Makefile
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_clock/ip-xact
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_clock/ip-xact/design.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_clock/rtl
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_clock/rtl/verilog
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_clock/rtl/verilog/syn
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_clock/rtl/verilog/syn/cde_clock_sys.v
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_clock/rtl/xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_clock/rtl/xml/cde_clock_sys.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_jtag
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_jtag/bin
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_jtag/bin/Makefile
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_jtag/ip-xact
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_jtag/ip-xact/design.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_jtag/rtl
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_jtag/rtl/verilog
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_jtag/rtl/verilog/syn
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_jtag/rtl/verilog/syn/cde_jtag_def.v
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_jtag/rtl/xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_jtag/rtl/xml/cde_jtag_def.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/bin
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/bin/Makefile
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/ip-xact
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/ip-xact/design.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/ip-xact/Nexys2_fpga_designCfg.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/ip-xact/Nexys2_fpga_jtag_designCfg.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_core.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_design.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_jtag_design.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_jtag_padring.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_padring.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/sim
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/sim/xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/sim/xml/fpga_jtag_padring_dut.design.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/sim/xml/fpga_jtag_padring_tb.params.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/sim/xml/fpga_padring_dut.design.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/sim/xml/fpga_padring_tb.params.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/jtag
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/busDef
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/busDef/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/busDef/xml/jtag_rpc.busDefinition.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/busDef/xml/jtag_rpc_rtl.abstractionDefinition.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/verilog/top
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/cde_sram.lint
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/cde_sram_be
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/cde_sram_be.top
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/cde_sram_def
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/cde_sram_def.top
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/cde_sram_dp
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/cde_sram_dp.top
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/write
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/write.be
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_be.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_dp.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/verilog/lint
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/verilog/lint/cde_sync.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/verilog/lint/cde_sync_with_hysteresis.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/verilog/lint/cde_sync_with_reset.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/xml/cde_sync_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/xml/cde_sync_with_hysteresis.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/xml/cde_sync_with_reset.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_core.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_default.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_irq_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_poll_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_irq_2_test.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_kim_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_tim_2.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_core.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_default.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_uart.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502/rtl/verilog/top.rtl
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502/rtl/xml/T6502_ctrl.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502/rtl/xml/T6502_def.design.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502/rtl/xml/T6502_def.xml
/socgen/trunk/projects/opencores.org/Nexys2
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/busDef
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/busDef/xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/busDef/xml/or1k_cpu.busDefinition.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/busDef/xml/or1k_cpu_rtl.abstractionDefinition.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/busDef/xml/or1k_dbg.busDefinition.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/busDef/xml/or1k_dbg_rtl.abstractionDefinition.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/busDef/xml/or1k_spr.busDefinition.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/busDef/xml/or1k_spr_rtl.abstractionDefinition.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_dbg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml/or1200_cache_data.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml/or1200_cache_inst.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_cfgr.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_dbg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_du.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_except.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_lsu.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_rf.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_sprs.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_spr_mux.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_fpu/rtl/xml/or1200_fpu_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml/or1200_mmu_data.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml/or1200_mmu_inst.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/rtl/xml/or1200_mult_mac_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/rtl/xml/or1200_pic_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/rtl/xml/or1200_pm_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/xml/or1200_qmem_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/rtl/xml/or1200_sb_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/rtl/xml/or1200_tt_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/xml/or1200_wb_biu_def.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/or1200_dbg_model/rtl/xml/or1200_dbg_model_def.xml
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/xml/adv_dbg_if_wb.xml
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/xml/adv_dbg_if_wb_cpu.xml
/socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if/rtl/xml/adv_dbg_if_wb_cpu2_jsp.xml
/socgen/trunk/projects/opencores.org/xfer/ip/minsoc/rtl/xml/minsoc_def.xml
/socgen/trunk/tools/verilog/gen_verilog
/socgen/trunk/tools/yp/hier_index.xml
/socgen/trunk/tools/yp/index.xml
/socgen/trunk/tools/yp/lib.pm

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