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[/] [socgen/] - Rev 127

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Last modification

  • Rev 127, 2013-05-23 00:00:03 GMT
  • Author: jt_eaton
  • Log message:
    final cleanup before DAC
Path
/socgen/trunk/Makefile
/socgen/trunk/projects/digilentinc.com/Nexys2/ip-xact/libraryCfg.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_clock/ip-xact/componentCfg.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_clock/rtl/xml/cde_clock_sys.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_jtag/ip-xact/componentCfg.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_jtag/rtl/xml/cde_jtag_def.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/ip-xact/componentCfg.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_core.xml
/socgen/trunk/projects/github.com/mor1kx/ip-xact/libraryCfg.xml
/socgen/trunk/projects/github.com/mor1kx/ip/Sim
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/bin
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/bin/Makefile
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/doc
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/doc/html
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/doc/png
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/doc/timing
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/ip-xact
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/ip-xact/componentCfg.xml
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/bin
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/bin/Makefile
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/icarus
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/icarus/or1200-basic_cap
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/icarus/or1200-basic_cap/dmp_define
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/icarus/or1200-basic_cap/test_define
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/icarus/or1200-basic_cap/wave.sav
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/icarus/or1200-basic_esp
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/icarus/or1200-basic_esp/dmp_define
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/icarus/or1200-basic_esp/test_define
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/icarus/or1200-basic_esp/wave.sav
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/icarus/or1200-basic_prontoesp
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/icarus/or1200-basic_prontoesp/dmp_define
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/icarus/or1200-basic_prontoesp/test_define
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/icarus/or1200-basic_prontoesp/wave.sav
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/icarus/or1200-cbasic
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/icarus/or1200-cbasic/dmp_define
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/icarus/or1200-cbasic/test_define
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/icarus/or1200-cbasic/wave.sav
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/testbenches
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/testbenches/verilog
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/testbenches/verilog/top.rtl
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/testbenches/verilog/top.vtb
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/testbenches/xml
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/testbenches/xml/Sim_bfm.design.xml
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/testbenches/xml/Sim_cappuccino_dut.params.xml
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/testbenches/xml/Sim_cappuccino_dutg.design.xml
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/testbenches/xml/Sim_cappuccino_lint.xml
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/testbenches/xml/Sim_cappuccino_tb.xml
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/testbenches/xml/Sim_espresso_dut.params.xml
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/testbenches/xml/Sim_espresso_dutg.design.xml
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/testbenches/xml/Sim_espresso_lint.xml
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/testbenches/xml/Sim_espresso_tb.xml
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/testbenches/xml/Sim_prontoespresso_dut.params.xml
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/testbenches/xml/Sim_prontoespresso_dutg.design.xml
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/testbenches/xml/Sim_prontoespresso_lint.xml
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/testbenches/xml/Sim_prontoespresso_tb.xml
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/verilator
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/verilator/inst_1_test
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/verilator/inst_1_test/dmp_define
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/sim/verilator/inst_1_test/wave.sav
/socgen/trunk/projects/github.com/mor1kx/ip/Sim/syn
/socgen/trunk/projects/github.com/mor1kx/ip/sys/ip-xact/componentCfg.xml
/socgen/trunk/projects/github.com/mor1kx/ip/sys/rtl/verilog/mor1kx_sys_cappuccino.v
/socgen/trunk/projects/github.com/mor1kx/ip/sys/rtl/verilog/mor1kx_sys_espresso.v
/socgen/trunk/projects/github.com/mor1kx/ip/sys/rtl/verilog/mor1kx_sys_prontoespresso.v
/socgen/trunk/projects/github.com/mor1kx/ip/sys/rtl/xml/sys_cappuccino.xml
/socgen/trunk/projects/github.com/mor1kx/ip/sys/rtl/xml/sys_espresso.xml
/socgen/trunk/projects/github.com/mor1kx/ip/sys/rtl/xml/sys_prontoespresso.xml
/socgen/trunk/projects/github.com/mor1kx/ip/sys/sim/icarus
/socgen/trunk/projects/github.com/mor1kx/ip/sys/sim/testbenches
/socgen/trunk/projects/github.com/mor1kx/ip/sys/sim/verilator
/socgen/trunk/projects/github.com/mor1kx/testbenches
/socgen/trunk/projects/github.com/mor1kx/testbenches/xml
/socgen/trunk/projects/opencores.org/cde/ip-xact/libraryCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_diff_testmux.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_dll.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_gater.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_sys.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_testmux.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/rtl/xml/cde_divider_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/rtl/xml/cde_fifo_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_in_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_rpc_in_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_rpc_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/testbenches/xml/cde_jtag_def_lint.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/testbenches/xml/cde_jtag_def_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/rtl/xml/cde_lifo_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_generic.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_ord_r4.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_serial.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_generic_lint.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_generic_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_ord_r4_lint.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_ord_r4_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_serial_lint.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_serial_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/rtl/xml/cde_prescale_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/xml/cde_reset_asyncdisable.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/xml/cde_reset_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/sim/testbenches/xml/cde_serial_both_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/sim/testbenches/xml/cde_serial_rcvr_lint.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/sim/testbenches/xml/cde_serial_xmit_lint.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/pad/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/pad/rtl/xml/cde_pad_in_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/pad/rtl/xml/cde_pad_od_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/pad/rtl/xml/cde_pad_out_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/pad/rtl/xml/cde_pad_se_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/pad/rtl/xml/cde_pad_tri_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/sram/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/array
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/copyright.v
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/lint
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/lint/sram_be.v
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/lint/sram_def.v
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/lint/sram_dp.v
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/sim
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/sim/sram_be.v
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/sim/sram_def.v
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/sim/sram_dp.v
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/sram.lint
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/sram_be.top
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/sram_def.top
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/sram_dp.top
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/syn
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/syn/sram_be.v
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/syn/sram_def.v
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/syn/sram_dp.v
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/write
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/write.be
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/xml/sram_be.xml
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/xml/sram_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/xml/sram_dp.xml
/socgen/trunk/projects/opencores.org/fpgas/ip-xact/libraryCfg.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_core.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_default.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_irq_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_poll_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_irq_2_test.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_kim_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_tim_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/icarus/kim_2/wave.sav
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/testbenches/xml/Nexys2_T6502_default_lint.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/testbenches/xml/Nexys2_T6502_default_tb.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_irq_2/verilog
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_irq_2/verilog/copyright.v
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_irq_2/xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_irq_2/xml/Nexys2_T6502_io_irq_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_poll_2/verilog
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_poll_2/verilog/copyright.v
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_poll_2/xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_poll_2/xml/Nexys2_T6502_io_poll_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_irq_2_test/verilog
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_irq_2_test/verilog/copyright.v
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_irq_2_test/xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_irq_2_test/xml/Nexys2_T6502_irq_2_test.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_kim_2/verilog
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_kim_2/verilog/copyright.v
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_kim_2/xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_kim_2/xml/Nexys2_T6502_kim_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_tim_2/verilog
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_tim_2/verilog/copyright.v
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_tim_2/xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_tim_2/xml/Nexys2_T6502_tim_2.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip-xact/libraryCfg.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_core.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_default.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_uart.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/testbenches/xml/Nexys2_minsoc_default_lint.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/testbenches/xml/Nexys2_minsoc_default_tb.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/syn/ise/Nexys2_minsoc_uart/verilog
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/syn/ise/Nexys2_minsoc_uart/verilog/copyright.v
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/syn/ise/Nexys2_minsoc_uart/xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/syn/ise/Nexys2_minsoc_uart/xml/Nexys2_minsoc_uart.xml
/socgen/trunk/projects/opencores.org/io/ip-xact/libraryCfg.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/rtl/xml/io_ext_mem_interface_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/sim/testbenches/xml/io_ext_mem_interface_def_lint.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/sim/testbenches/xml/io_ext_mem_interface_def_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_gpio/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/io/ip/io_gpio/rtl/xml/io_gpio_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_gpio/sim/testbenches/xml/io_gpio_def_lint.xml
/socgen/trunk/projects/opencores.org/io/ip/io_gpio/sim/testbenches/xml/io_gpio_def_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_gpio.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_mouse.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/sim/testbenches/xml/io_module_def_lint.xml
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