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[/] [uart16550/] [tags/] [rel_3/] - Rev 79

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Last modification

Rev 79, 2002-07-22 23:02:23 GMT
Author: gorban
Log message:
Bug Fixes:
* Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
Problem reported by Kenny.Tung.
* Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.

Improvements:
* Made FIFO's as general inferrable memory where possible.
So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
This saves about 1/3 of the Slice count and reduces P&R and synthesis times.

* Added optional baudrate output (baud_o).
This is identical to BAUDOUT* signal on 16550 chip.
It outputs 16xbit_clock_rate - the divided clock.
It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.

Path
/trunk/rtl/verilog/raminfr.v
/trunk/rtl/verilog/uart_debug_if.v
/trunk/rtl/verilog/uart_defines.v
/trunk/rtl/verilog/uart_receiver.v
/trunk/rtl/verilog/uart_regs.v
/trunk/rtl/verilog/uart_rfifo.v
/trunk/rtl/verilog/uart_tfifo.v
/trunk/rtl/verilog/uart_top.v
/trunk/rtl/verilog/uart_transmitter.v
/trunk/rtl/verilog/uart_wb.v

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