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https://opencores.org/ocsvn/uart16550/uart16550/trunk
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[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 60
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Last modification
- Rev 60, 2001-12-17 10:14:43 GMT
- Author: mohor
- Log message:
- Things related to msr register changed. After THRE IRQ occurs, and one
character is written to the transmit fifo, the detection of the THRE bit in the
LSR is delayed for one character time.
