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[/] - Rev 48

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Last modification

Rev 48, 2001-12-03 21:44:29 GMT
Author: gorban
Log message:
Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.

Path
/trunk/bench/verilog/uart_test.v
/trunk/bench/verilog/wb_mast.v
/trunk/doc/src/UART_spec.doc
/trunk/doc/UART_spec.pdf
/trunk/rtl/verilog/uart_defines.v
/trunk/rtl/verilog/uart_receiver.v
/trunk/rtl/verilog/uart_regs.v
/trunk/rtl/verilog/uart_top.v
/trunk/rtl/verilog/uart_transmitter.v
/trunk/rtl/verilog/uart_wb.v
/trunk/sim/rtl_sim/bin/sim.tcl

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