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[/] [wiegand_ctl/] - Rev 5

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Last modification

  • Rev 5, 2015-02-06 22:49:38 GMT
  • Author: jeaander
  • Log message:
    testbench works fine; Wiegand TX needs WB intf connected to remainder of controller
Path
/wiegand_ctl/trunk/sim
/wiegand_ctl/trunk/sim/compile_hw.do
/wiegand_ctl/trunk/sim/compile_hw.do.bak
/wiegand_ctl/trunk/sim/compile_hw.tcl
/wiegand_ctl/trunk/sim/modelsim.ini
/wiegand_ctl/trunk/sim/vsim.do
/wiegand_ctl/trunk/sim/vsim.wlf
/wiegand_ctl/trunk/sim/wave.do
/wiegand_ctl/trunk/sim/wiegand_tb.cr.mti
/wiegand_ctl/trunk/sim/wiegand_tb.mpf
/wiegand_ctl/trunk/sim/wlft6g1vah
/wiegand_ctl/trunk/sim/work
/wiegand_ctl/trunk/sim/work/custom_fifo_dp
/wiegand_ctl/trunk/sim/work/custom_fifo_dp/verilog.prw
/wiegand_ctl/trunk/sim/work/custom_fifo_dp/verilog.psm
/wiegand_ctl/trunk/sim/work/custom_fifo_dp/_primary.dat
/wiegand_ctl/trunk/sim/work/custom_fifo_dp/_primary.dbs
/wiegand_ctl/trunk/sim/work/custom_fifo_dp/_primary.vhd
/wiegand_ctl/trunk/sim/work/fifo_wieg
/wiegand_ctl/trunk/sim/work/fifo_wieg/verilog.prw
/wiegand_ctl/trunk/sim/work/fifo_wieg/verilog.psm
/wiegand_ctl/trunk/sim/work/fifo_wieg/_primary.dat
/wiegand_ctl/trunk/sim/work/fifo_wieg/_primary.dbs
/wiegand_ctl/trunk/sim/work/fifo_wieg/_primary.vhd
/wiegand_ctl/trunk/sim/work/mem_byte
/wiegand_ctl/trunk/sim/work/mem_byte/verilog.prw
/wiegand_ctl/trunk/sim/work/mem_byte/verilog.psm
/wiegand_ctl/trunk/sim/work/mem_byte/_primary.dat
/wiegand_ctl/trunk/sim/work/mem_byte/_primary.dbs
/wiegand_ctl/trunk/sim/work/mem_byte/_primary.vhd
/wiegand_ctl/trunk/sim/work/testbench_top
/wiegand_ctl/trunk/sim/work/testbench_top/verilog.prw
/wiegand_ctl/trunk/sim/work/testbench_top/verilog.psm
/wiegand_ctl/trunk/sim/work/testbench_top/_primary.dat
/wiegand_ctl/trunk/sim/work/testbench_top/_primary.dbs
/wiegand_ctl/trunk/sim/work/testbench_top/_primary.vhd
/wiegand_ctl/trunk/sim/work/testcase_1
/wiegand_ctl/trunk/sim/work/testcase_1/verilog.prw
/wiegand_ctl/trunk/sim/work/testcase_1/verilog.psm
/wiegand_ctl/trunk/sim/work/testcase_1/_primary.dat
/wiegand_ctl/trunk/sim/work/testcase_1/_primary.dbs
/wiegand_ctl/trunk/sim/work/testcase_1/_primary.vhd
/wiegand_ctl/trunk/sim/work/wb_interface_wieg
/wiegand_ctl/trunk/sim/work/wb_interface_wieg/verilog.prw
/wiegand_ctl/trunk/sim/work/wb_interface_wieg/verilog.psm
/wiegand_ctl/trunk/sim/work/wb_interface_wieg/_primary.dat
/wiegand_ctl/trunk/sim/work/wb_interface_wieg/_primary.dbs
/wiegand_ctl/trunk/sim/work/wb_interface_wieg/_primary.vhd
/wiegand_ctl/trunk/sim/work/wiegand_tx_top
/wiegand_ctl/trunk/sim/work/wiegand_tx_top/verilog.prw
/wiegand_ctl/trunk/sim/work/wiegand_tx_top/verilog.psm
/wiegand_ctl/trunk/sim/work/wiegand_tx_top/_primary.dat
/wiegand_ctl/trunk/sim/work/wiegand_tx_top/_primary.dbs
/wiegand_ctl/trunk/sim/work/wiegand_tx_top/_primary.vhd
/wiegand_ctl/trunk/sim/work/_info
/wiegand_ctl/trunk/sim/work/_temp
/wiegand_ctl/trunk/sim/work/_temp/vlog4nj5h6
/wiegand_ctl/trunk/sim/work/_temp/vlog4vwbr6
/wiegand_ctl/trunk/sim/work/_temp/vlog5anz03
/wiegand_ctl/trunk/sim/work/_temp/vlog5ik496
/wiegand_ctl/trunk/sim/work/_temp/vlog9dyh3n
/wiegand_ctl/trunk/sim/work/_temp/vlog9jd6qg
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/wiegand_ctl/trunk/sim/work/_temp/vlogg1t4dh
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/wiegand_ctl/trunk/sim/work/_temp/vlogtft2zy
/wiegand_ctl/trunk/sim/work/_temp/vlogvrtfvn
/wiegand_ctl/trunk/sim/work/_temp/vlogw7h83s
/wiegand_ctl/trunk/sim/work/_temp/vlogx1mdnv
/wiegand_ctl/trunk/sim/work/_temp/vlogx6zd8m
/wiegand_ctl/trunk/sim/work/_temp/vlogxsfgbg
/wiegand_ctl/trunk/sim/work/_temp/vlogzzdcwi
/wiegand_ctl/trunk/sim/work/_vmake

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