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OPB interface to Memory Controller IP Core
by Unknown on Feb 2, 2004 |
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Hey everyone,
I am currently working on a project for my engineering studies, and I am in need of a DDR memory controller, that would understand burst reads. From what I can read from the documentation of Rudolf Usselmann's memory controller IP core, it appears to be what I am looking for, except that I am using a Xilinx MicroBlaze CPU, and I need to connect the controller to the OPB bus. From what I can see in the Verilog code (which isn't that much, I basically don't understand any Verilog, only VHDL), it appears to be fairly easy to replace the wishbone interface with a OPB (or OPB IPIF) interface. Is this correct, or have I overlooked something? As I mentioned Verilog is not my "first language", so I was wondering if there is some way to mix VHDL and Verilog in the same core? Another thing, have anyone ever worked on a generic bridge between wishbone and OPB? It doesn't look that difficult to implement, as the busses seem fairly similar. -- First everyone believes that something cannot be done. Then some fool shows it might be not be impossible. Then a scientist shows it is theoretically possible, and finally an engineer shows how to do it. Then it seems obvious. |
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OPB interface to Memory Controller IP Core
by Unknown on Feb 2, 2004 |
Not available! | ||
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On Mon, 2004-02-02 at 18:32, Anders Hellerup Madsen wrote:
Hey everyone,
I am currently working on a project for my engineering studies, and I am in need of a DDR memory controller, that would understand burst reads. From what I can read from the documentation of Rudolf Usselmann's memory controller IP core, it appears to be what I am looking for, except that I am using a Xilinx MicroBlaze CPU, and I need to connect the controller to the OPB bus. From what I can see in the Verilog code (which isn't that much, I basically don't understand any Verilog, only VHDL), it appears to be fairly easy to replace the wishbone interface with a OPB (or OPB IPIF) interface. Is this correct, or have I overlooked something? Just a tiny little thing: It does not support DDR memories !
As I mentioned Verilog is not my "first language", so I was wondering if
Regards,
rudi
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there is some way to mix VHDL and Verilog in the same core? Another thing, have anyone ever worked on a generic bridge between wishbone and OPB? It doesn't look that difficult to implement, as the busses seem fairly similar. |
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OPB interface to Memory Controller IP Core
by Unknown on Feb 2, 2004 |
Not available! | ||
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Rudolf Usselmann wrote:
From what I can see in the Verilog code (which isn't that much, I
basically don't understand any Verilog, only VHDL), it appears to be fairly easy to replace the wishbone interface with a OPB (or OPB IPIF) interface. Is this correct, or have I overlooked something? Just a tiny little thing: It does not support DDR memories ! Ah. It seems I am momentarily unable to read and write at the moment. This usually doesn't happen once I have had the first two cups of coffe. Sorry for wasting everyones time. -- First everyone believes that something cannot be done. Then some fool shows it might be not be impossible. Then a scientist shows it is theoretically possible, and finally an engineer shows how to do it. Then it seems obvious. |
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OPB interface to Memory Controller IP Core
by Unknown on Feb 2, 2004 |
Not available! | ||
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Since you are targeting a Xilinx device, take a look at the application
notes on their web site. Xilinx has several application notes that include synthesizable code for DDR controllers. Take a look at: XAPP200 100 MHz DDR controller XAPP253 200 MHz DDR controller XAPP266 DDR Fast Cycle Ram controller XAPP608 DDR to USB 2.0 I believe that these all had VHDL code instead of Verilog. Regards, John McCaskill |
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