I have been looking in on what you are saying about fifo.

I agree make it clear where the split is, letting the fifo be the
point of
interconnection.

A good example of a programmable fifo can be found on the Xilinx
web pages
that are very easily changeable.

i.e databus size, depth, speed and also, area. (1 or 2 clocks).
Also can be changed to use xilinx block ram or distributed.

They have already been used and proven.

I have one examples, slightly different, both dual port.

Note these are slightly modified due our own coding methods where
we
specify.

This fifo is an 8-bit * 511 location (depth) dual port synchronous
clock.
See Xilinx web site for more info.



LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY fifo_9_8 IS
PORT(
ra_sys : IN STD_LOGIC ;
-- System reset internally generated.
ckr_sys : IN STD_LOGIC ;
-- System
clock.

wrd_rs_sys : IN STD_LOGIC ;
--
Synchronous reset rising edge triggered.

ip_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
-- Fifo
input data.
ip_write_en : IN STD_LOGIC ;
-- Fifo
input enable.

op_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
-- Fifo
output data.
ip_read_en : IN STD_LOGIC ;
-- Fifo
output enable.
op_full : OUT STD_LOGIC ;
-- Fifo full signal.
op_empty : OUT

-- Fifo empty signal.
op_addr_pty : OUT STD_LOGIC_VECTOR(8

-- Fifo pointer output.

);
END fifo_9_8;

ARCHITECTURE asic OF fifo_9_8 IS

--------------------------------------------------------------------

------------------------------------------
-- Component declaration.
COMPONENT dpram_9_8_top
PORT(
ckr_sys : IN STD_LOGIC ;
--
System clock.

ip_porta_addr : IN STD_LOGIC_VECTOR(8

-- Write side address.
ip_porta_data : IN STD_LOGIC_VECTOR(7

-- Write side data.
ip_porta_en : IN STD_LOGIC
; -- Write side enable.

ip_portb_addr : IN STD_LOGIC_VECTOR(8

-- READ side address.
op_portb_data : OUT STD_LOGIC_VECTOR(7

-- READ side data.
ip_portb_en : IN STD_LOGIC
-- READ enable.

);
END COMPONENT;




--------------------------------------------------------------------

------------------------------------------
-- Signal declaration.
SIGNAL s_write_addr : STD_LOGIC_VECTOR(8

;
-- Write side address.
SIGNAL s_write_data :

; -- Write side data.

SIGNAL s_read_addr :

; -- READ side address.
SIGNAL s_read_data :

; -- READ side data.

SIGNAL s_empty : STD_LOGIC
; -- Empty flag.
SIGNAL s_full : STD_LOGIC
; -- Full flag.

SIGNAL s_read_en : STD_LOGIC
; -- READ side address.
SIGNAL s_write_en : STD_LOGIC
; -- READ side data.

SIGNAL s_read_ctrl : STD_LOGIC
; -- READ side address.
SIGNAL s_write_ctrl : STD_LOGIC
; -- READ side data.

SIGNAL s_fifo_cnt :

; -- Fifo counter.


SIGNAL s_read_lfsr_fb :

;
-- Read counter LFSR feedback logic.
SIGNAL s_write_lfsr_fb :

;
-- Write counter LFSR feedback logic.

SIGNAL s_read_bank0 : STD_LOGIC
; -- Read counter bank zero flag.
SIGNAL s_read_bit0 : STD_LOGIC
; -- Read counter bit zero flag.

SIGNAL s_read_bankF : STD_LOGIC
; -- Read counter bank F flag.

SIGNAL s_rs_sy : STD_LOGIC
; -- Reset signal.
SIGNAL s_rs_sy_1ff : STD_LOGIC
; -- Reset signal delayed.
SIGNAL s_rs_sy_re : STD_LOGIC
; -- Reset signal rising edge delayed.



BEGIN

--------------------------------------------------------------------

------------------------------------------
-- Synchronous reset generation.

sync_reset_gen : PROCESS ( ra_sys, ckr_sys )
BEGIN
IF (ra_sys = '1') THEN
s_rs_sy s_rs_sy_1ff s_rs_sy_re ELSIF ((ckr_sys'EVENT) AND (ckr_sys = '1')) THEN
s_rs_sy s_rs_sy_1ff s_rs_sy_re END IF;
END PROCESS;





--------------------------------------------------------------------

------------------------------------------

-- Instance the Dual port memory.
dpram_9_8_top_i0 : dpram_9_8_top
PORT MAP (
ckr_sys => ckr_sys , --
System clock.

ip_porta_addr => s_write_addr , --

side address.
ip_porta_data => s_write_data , --

side data.
ip_porta_en => s_write_en , --

side enable.

ip_portb_addr => s_read_addr , --

side address.
op_portb_data => s_read_data , --

side data.
ip_portb_en => s_read_en --

enable.

);



-- Read enable logic.
s_read_en Only read
when not empty.


-- Write enable logic.
s_write_en
-- Only write when not full.


-- Empty flag generation.
-- Set when on the next clock cycle, write_ctrl is low,
-- and either the fifo_pty is equal to 0,
-- or it is equal to 1 and read ctrl is high (about to go e,pty)
empty_gen : PROCESS ( ra_sys, ckr_sys )
BEGIN
IF (ra_sys = '1') THEN
s_empty ELSIF ((ckr_sys'EVENT) AND (ckr_sys = '1')) THEN
IF ( s_rs_sy_re = '1' ) THEN
s_empty ELSE
s_empty

s_read_bit0 OR s_read_ctrl ) );
END IF;
END IF;
END PROCESS;

s_read_bit0 s_read_bank0 ) ELSE '0';




-- Full flag generation.
-- Set on reset, but cleard on first valid clock edge that reset
is
removed.
-- Or when on the next clock cycle, read_ctrl is low, and
-- either fifo_cnt is equal to 0x1FF, or it is equal to ox1FE and
the
write_ctrl
-- is high, (about to go full).
full_gen : PROCESS ( ra_sys, ckr_sys )
BEGIN
IF (ra_sys = '1') THEN
s_full ELSIF ((ckr_sys'EVENT) AND (ckr_sys = '1')) THEN
IF ( s_rs_sy_re = '1' ) THEN
s_full ELSE
s_full NOT(s_read_bit0) OR s_write_ctrl) );
END IF;
END IF;
END PROCESS;


s_read_bankF ELSE '0';









-- Read counter.
-- This uses a LFSR, which results in a very fast counter at the
expense of
a single location.

s_read_lfsr_fb The LFSR
feedback signal.

read_cnt : PROCESS ( ra_sys, ckr_sys )
BEGIN
IF (ra_sys = '1') THEN
s_read_addr '0') ;
ELSIF ((ckr_sys'EVENT) AND (ckr_sys = '1')) THEN
IF ( s_rs_sy_re = '1' ) THEN
s_read_addr '0') ;
ELSIF ( s_read_en = '1' ) THEN
s_read_addr

;
-- Shift register enable of s_read_ctrl.
END IF;
END IF;
END PROCESS;




-- Write counter.
-- This uses a LFSR, which results in a very fast counter at the
expense of
a single location.

s_write_lfsr_fb -- The LFSR
feedback signal.

write_cnt : PROCESS ( ra_sys, ckr_sys )
BEGIN
IF (ra_sys = '1') THEN
s_write_addr '0') ;
ELSIF ((ckr_sys'EVENT) AND (ckr_sys = '1')) THEN
IF ( s_rs_sy_re = '1' ) THEN
s_write_addr '0') ;
ELSIF ( s_write_en = '1' ) THEN
s_write_addr s_write_lfsr_fb ; -- Shift register enable of s_write_ctrl.
END IF;
END IF;
END PROCESS;




-- Generate the fifo count.
-- Used to determine how full the FIFO is, based on a counter
-- that keeps track of how many words are in the FIFO.
-- Also used to generate Full and Empty flags.
fifo_cnt : PROCESS ( ra_sys, ckr_sys )
BEGIN
IF (ra_sys = '1') THEN
s_fifo_cnt '0') ;
ELSIF ((ckr_sys'EVENT) AND (ckr_sys = '1')) THEN
IF ( s_rs_sy_re = '1' ) THEN
s_fifo_cnt '0') ;
ELSIF ( ((s_read_en = '0') AND ( s_write_en = '1' )) OR
((s_read_en = '1') AND ( s_write_en = '0')) ) THEN
IF ( s_write_en = '1' ) THEN
s_fifo_cnt Increment the counter.
ELSE
s_fifo_cnt Increment the counter.
END IF;
END IF;
END IF;
END PROCESS;
-- This is the slower bit of logic, but only used to
generate the full, empty flag, not memory decode etc.





-- Assign inputs and outputs.

s_write_data s_write_ctrl s_read_ctrl
op_data op_full op_empty op_addr_pty


END asic;





And the dual port memory that can be easily changed.


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;



ENTITY dpram_9_8_top IS
PORT(
ckr_sys : IN STD_LOGIC
;
-- System clock.

ip_porta_addr : IN STD_LOGIC_VECTOR(8

-- Write side address.
ip_porta_data : IN STD_LOGIC_VECTOR(7

-- Write side data.
ip_porta_en : IN STD_LOGIC
; -- Write side enable.

ip_portb_addr : IN STD_LOGIC_VECTOR(8

-- READ side address.
op_portb_data : OUT STD_LOGIC_VECTOR(7

-- READ side data.
ip_portb_en : IN STD_LOGIC
-- READ enable.

);
END dpram_9_8_top;

ARCHITECTURE asic OF dpram_9_8_top IS

-- define_attribute {ram_dp_9_8|s_portb_data[7:0]}

"block_ram"
-- define_attribute {ram_dp_9_8|s_portb_data[7:0]} syn_ramstyle
"registers"


--------------------------------------------------------------------

-------------------------------------------------------------

--------------------------------------------------------------------

-------------------------------------------------------------
-- Components.


--------------------------------------------------------------------

-------------------------------------------------------------
-- Signal declaration.

SIGNAL s_portb_data : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL s_portb_data_1ff : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL ip_portb_addr_reg : STD_LOGIC_VECTOR(8 downto 0);

-- Define memory.
type mem_type is array (511 downto 0) of STD_LOGIC_VECTOR (7

0);

signal mem : mem_type;


--------------------------------------------------------------------

-------------------------------------------------------------

--------------------------------------------------------------------

-------------------------------------------------------------
BEGIN

process(ckr_sys)
begin
if ( ckr_sys'EVENT AND ckr_sys ='1' ) then
if (ip_porta_en = '1') then
mem(conv_integer(ip_porta_addr)) end if;
end if;
end process;

op_portb_data

process(ckr_sys) -- Coding for block memory inference
begin
if ( ckr_sys'EVENT AND ckr_sys ='1' ) then
-- This is registered only to infer block remory.
ip_portb_addr_reg end if;
end process;




process(ckr_sys) -- This is

design. begin if ( ckr_sys'EVENT AND ckr_sys ='1' ) then s_portb_data_1ff gmp216 at i... ] Sent: Thursday, January 20, 2000 2:26 AM To: cores at o... Subject: Re: [Re: [oc] PCI sub projects] > So... how about making a clear boundary > between the FIFO and the AMBA interface in > the design? If the FIFO were well enough specified that it could serve as

interface
by itself, then that would solve this problem. Not all designs
will
want
AMBA.

> CONFIG
> PCI FIFO AMBA
> STATE MACHINE
>
> The AMBA could be removed if the user don't
> need / don't want to use. But then he
> have to design the interface directly
> connect to the FIFO and the state machines.

How about:

CONFIG
PCI STATE MACHINE FIFO

There is no reason for the state machines or anything else to

externally
visible. Everything can be done through the FIFO. If our FIFO
interface
is generic enough, then we only need to design the FIFO
AMBA
block
once, and use it for all of our cores.

---
greg

-----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of madan at swissinfo.org Sent: Wednesday, February 04, 2004 7:18 AM To: cores at opencores.org Subject: RE: [Re: [oc] PCI sub projects] Dear Sir, I am using the 2kdeepx16 memory as FIFO. for a control circuit , i am using LFSR with a tap at (11,9) as per application note xapp052.pdf. But I have problem that if I would like filling all the 2kx16 locations the pattern is repetitive and hence locations are over written results in no match of read out data from the FIFO. Please guide me regarding this to fix. Thanks in Advance, Madan ----- Original Message ----- From: Lee Ainscough Lee.Ainscough at p... > To: "'cores at o... '" cores at o... > Date: Thu, 20 Jan 2000 07:44:42 -0000 Subject: RE: [Re: [oc] PCI sub projects]
STD_LOGIC ;

DOWNTO 0)

--------

DOWNTO 0) ;

DOWNTO 0) ;

DOWNTO 0) ;

DOWNTO 0) ;

--------

DOWNTO 0)

STD_LOGIC_VECTOR(7 DOWNTO 0)

STD_LOGIC_VECTOR(8 DOWNTO 0)

STD_LOGIC_VECTOR(7 DOWNTO 0)

STD_LOGIC_VECTOR(8 DOWNTO 0)

STD_LOGIC

STD_LOGIC

--------

--------

Write

Write

Write

READ

READ

READ

(

s_read_lfsr_fb

DOWNTO 0) ;

DOWNTO 0) ;

DOWNTO 0) ;

DOWNTO 0) ;

syn_ramstyle

--------

--------

--------

downto

--------

--------

specific to the

an

be
_______________________________________________ http://www.opencores.org/mailman/listinfo/cores