Hi,

I have a couple of questions concerning the wishbone bus specification, I hope this is
the right place to ask them.

I am trying to implement a wishbone-based system which uses a VME-wishbone
bridge as the bus master. This part works fine. One of the slaves has significant
latency in terms of the ack response (it has to fetch data from another FPGA on my
board over a serial bus).

My first question is: there appears to be no way for my slave to detect if a cycle on
the bus has been timed out either by the wishbone arbiter or the VMEbus. In
principle, the cycle could be timed out, and the master could re-present a new cycle
on the bus without deasserting CYC/STB and without me asserting ACK. This is clearly
bad news. Is there any recommendation on how to implement a wishbone bus
timeout in a way that avoids this? I am keen to avoid any possibility of bus hangups.

The second question: the wishbone spec allows slaves which support single-cycle bus
cycles, but not block transfer cycles. What is the correct behaviour of such a slave
when presented with a block transfer cycle, i.e. CYC/STB are not deasserted after
ACK is asserted?

Thanks for any help you can offer.

Regards,

Dave Newbold