Hi kuzmi4!
I do have one design with Xilinx natives using designated block ram on Spartan 6.

Now I tried to put one design together as you mentioned. Using only sram4EN(datamem), sram(imem). Did you change sram(imem) for reading by removing dat_i and wre_i and only read in behavioral part? Because if I do errors pop up!

Regards tribbiani!

Hi tribbiani,

Actually, if you will simply remove "dat_i" and "wre_i" ports - Vivado will optimize this RAM. But if you have {Init-From-File}-logic with these 2 ports tight LOW, like in testbench,vhd -> there will be no problems with Vivado synth.

I did minor modifications for sram.vhd:
...
entity sram is generic
(
FNAME : string;
WIDTH : positive := 32;
SIZE : positive := 16
);
...
type ram_type is array(2 ** SIZE - 1 downto 0) of std_logic_vector(WIDTH - 1 downto 0);
--
impure function InitRamFromFile (RamFileName : in string) return ram_type is
FILE ramfile : text is in RamFileName;
variable RamFileLine : line;
variable ram : ram_type;
variable i : natural := 0;
begin
while not endfile(ramfile) loop
readline(ramfile, RamFileLine);
hread(RamFileLine, ram(i));
i := i + 1;
end loop;
return ram;
end function;
--
signal ram : ram_type := InitRamFromFile(FNAME);
...

And instantiation in Processor-Unit module:
...
imem : sram
generic map
(
FNAME => "rom.mem",
WIDTH => CFG_IMEM_WIDTH,
SIZE => rom_size - 2
)
...
Where "rom.mem" file generated using {../trunk/sw/util/..}-apps.

Hi kuzmi4 ! I will try to do your approach. sram adjusted for read only. Because of this I changed the ports of sram. sram4EN instantiate sram and here all ports are used, that creates a conflict:

mem: for i in 0 to WIDTH/8 - 1 generate
mem : sram generic map
(
WIDTH => 8,
SIZE => SIZE
)
port map
(
dat_o => dat_o((i+1)*8 - 1 downto i*8),
dat_i => dat_i((i+1)*8 - 1 downto i*8),
adr_i => adr_i,
wre_i => wre_i(i),
ena_i => ena_i,
clk_i => clk_i
);
end generate;
So sram is renamed to imem and a new component is added to stdpkg. Just some debugging needs to be done with some missing signals.

Did you solve it in a similar way?, and some words on how to use data init via MEM-files / would be greatly appreciated. Looking forward to program the circuit:)

-------------------- module inst used now ---------------------
sram_4en0 : sram_4en generic map
(
WIDTH => 32,
SIZE => 16
)


port MAP
(

dat_o =>s_dmem_i(0).dat_i,---- connect to address_decoder
dat_i =>s_dmem_o(0).dat_o,
adr_i => s_dmem_o(0).adr_o,--
wre_i => s_dmem_o(0).sel_o, --s_dmem_o(0).sel_o,-- connect for byte(3 downto 0)
ena_i => s_dmem_o(0).ena_o, --connect up to address_decoder logic
clk_i =>wb_i.clk_i
);
-----------------
imem0 :imem generic map -- instruction mem connect to core
(
WIDTH => 32,
SIZE => 16
)
port map
(
dat_o =>imem_i.dat_i,
--dat_i => dat_i,
adr_i =>imem_o.adr_o,
-- wre_i =>wre_i ,
ena_i =>imem_o.ena_o,
clk_i =>wb_i.clk_i --
);
------------------------------------------------------------------------
Best regards tribbiani!

Hi tribbiani,

You see, like I told you before -> you can not simply delete "dat_i" and "wre_i" ports for {sram.vhd}. And one of the reasons -> because you need this module for "sram_4en" module:
- after your sw-app compiled, linker located some data (NONE ZERO, required for processor to start correct execution of sw-app) in Data memory-region ("dram" module).
And because you have {sram.vhd} instantiation in {sram_4en.vhd} - you can not delete "dat_i" and "wre_i" ports in {sram.vhd}.
But now you have modified version of {sram.vhd} ("FNAME" parameter present), so modification for {sram_4en.vhd} will look, for example, like this :
..
architecture arch of sram_4en is
type type_name is array (0 to 3) of string(1 to 8);
constant ram_fname : type_name := ("rom0.mem", "rom1.mem", "rom2.mem", "rom3.mem");
...
mem : sram
generic map
(
FNAME => ram_fname(i),
WIDTH => 8,
SIZE => SIZE
)
...

hi kuzmi4! Did try to implement as you described. sram4EN is okay, do get problems with sram. sram is used in sram4EN also:
-------------------------------------
mem : sram generic map
(
WIDTH => 8,
SIZE => SIZE
)
------------------------------------------

so if I change ports in sram to dat_o,adr_i, ena_i and clk_i it violates sram4EN use of component.

Did create new component imem instantiated in top entity, component declared in std.pkg + new entity imem. Imem does not show up in RTL-view. Did clean up project files.
There is something I am missing! Please give a pointer:)

Regards Tribbiani!

------------ imem ----------------
component imem generic -- custom
(
WIDTH : positive;
SIZE : positive
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
--dat_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
-- wre_i : in std_logic;
ena_i : in std_logic;
clk_i : in std_logic

);
end component;
-----------------------------------------------------------------------------------

-------------------- top entity ---------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;


entity top_with_imem is generic
(
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_DEBUG : boolean := CFG_DEBUG;
CFG_NUM_SLAVES : positive := CFG_NUM_SLAVES

);

port
(
wb_o : out wb_mst_out_type;
wb_i : in wb_mst_in_type


);
end top_with_imem;


architecture Behavioral of top_with_imem is
---- add internal signals for new architecture
signal dmem_i : dmem_in_type;
signal dmem_o : dmem_out_type;
signal imem_o : imem_out_type;
signal imem_i : imem_in_type;
signal m_dmem_i : dmem_in_type;

signal s_dmem_o : dmem_out_array_type(2 - 1 downto 0);
signal m_dmem_o : dmem_out_type;
signal s_dmem_i : dmem_in_array_type(2 - 1 downto 0);
signal s_dmem_i_ena_i : dmem_in_array_type(2 - 1 downto 0);--signal for read of datamem
--signal wb_o : wb_mst_out_type;
--signal wb_i_reset : std_logic;
--------------------------- for debugging --------
--constant size : integer := 2;
--constant width : integer := 32;
--signal adr_i : std_logic_vector(31 downto 0);
signal sel_o : std_logic_vector(3 downto 0);
signal ena_o : std_logic;

--signal read_datamem_ena_i: dmem_in_array_type(2 - 1 downto 0);
-------------------------------------------------


begin

core0 : core generic map
(
G_INTERRUPT => G_INTERRUPT,
G_USE_HW_MUL => G_USE_HW_MUL,
G_USE_BARREL => G_USE_BARREL,
G_DEBUG => G_DEBUG
)
port map
(
imem_o => imem_o,
dmem_o => dmem_o,
imem_i => imem_i,
dmem_i => dmem_i,
int_i => wb_i.int_i,
rst_i => wb_i.rst_i,
clk_i => wb_i.clk_i
);


-------------- address_decoder added ---------------------------
core_address_decoder0: core_address_decoder generic map
(
G_NUM_SLAVES =>2 --G_NUM_SLAVES
)

port map
(
m_dmem_i => dmem_i,--connect up to core
s_dmem_o => s_dmem_o,
m_dmem_o => dmem_o,--connect up to core
s_dmem_i => s_dmem_i,
--s_dmem_i(0).ena_i =>s_dmem_i(0).ena_i,-- connect to logic for read datamem
clk_i => wb_i.clk_i
);



wb_adapter0 : core_wb_adapter port map
(
dmem_i => s_dmem_i(1),-- connect up to address_decoder
wb_o => wb_o,
dmem_o => s_dmem_o(1),
wb_i => wb_i
);
-----------------------------------------------

--
imem0 :imem generic map -- instruction mem connect to core
(
WIDTH => 32,
SIZE => 16
)
port map
(

dat_o =>imem_i.dat_i,
--dat_i => dat_i,
adr_i =>imem_o.adr_o,
-- wre_i =>wre_i ,
ena_i =>imem_o.ena_o,
clk_i =>wb_i.clk_i --
);



--sram0 : sram1 generic map
-- (
-- WIDTH => 32,
-- SIZE => 16
-- )
--
-- PORT MAP
-- (
-- imem_i => imem_i,
-- imem_o => imem_o,
-- clk_i => wb_i.clk_i
--
-- );

sram_4en0 : sram_4en generic map
(
WIDTH => 32,
SIZE => 16
)


port MAP
(

dat_o =>s_dmem_i(0).dat_i,---- connect to address_decoder
dat_i =>s_dmem_o(0).dat_o,
adr_i => s_dmem_o(0).adr_o,--
wre_i => s_dmem_o(0).sel_o, --s_dmem_o(0).sel_o,-- connect for byte(3 downto 0)
ena_i => s_dmem_o(0).ena_o, --connect up to address_decoder logic
clk_i =>wb_i.clk_i
);
--end generate;

end Behavioral;

Sorry did not see your answer from mars 3, vmware and to many browsers constantly open, refresh is a good thing.I will study your answers.

Thank you kuzmi4.

Hi tribbiani,

Actually, some days ago, I made some preparation to my next step with OC project, so you can find tested MB-Lite project here:
http://opencores.org/ocsvn/1g_ethernet_dpi/1g_ethernet_dpi/tags/vmblite_base
This project covers MB-Lite processor-unit construction, instruction-ram initialization, etc.
(in plans: add Etherent MAC and test network verification idea with completely OC-based system)

Great! Very helpful kuzmi4:) Almost there!!!

Did use cygwin in sw/util folder. make all created applications files of all the .c files. Did try to execute them with cygwin it did not work.


Did you use cygwin to create mem files?

Best regards tribbiani!!

Hi tribbiani,

This project done under Linux OS (Ubuntu 14LTS x64). I have no idea how it will work under Win-cygwin.

Hi kuzmi4! Some questions:
when you executed make in sw/util did you get application files of the respective .c files?

What did you do with applications files and did they create .mem files to init memory?

Best regards Tribbiani:)

I filled all rom files with 32-bit data and no @00000000 or comment in the beginning, it worked.

Tribbiani

Hi kuzmi4!
I am doing debugging and two things comes up.

1. s_dmem_i(0)_ena_i from datamem to address decoder is not connected in RTL, but only given value '1' in signal assignment.

2. In Map Report
core0/fetch0/Madd_r_program_counter[31]_GND_12_o_add_2_OUT_cy_rt downto 1 and
core0/fetch0/Madd_r_program_counter[31]_GND_12_o_add_2_OUT_xor_rt

are redundant and optimized away.

Do you have the same messages in your design, and can the first one be ignored?

Best regards tribbiani!

Hi tribbiani,

1) Code:
...
s_dmem_i(0).ena_i ...
I took from "../trunk/designs/core_decoder_wb/testbench.vhd" file of MB-Lite project. This signal related to {core_address_decoder} module.
Details of "core_address_decoder.vhd" you can find in "../trunk/doc/thesis.pdf", Figure 3.11: Design of the MB-Lite address decoder implemented with two slaves.
In short -> you have no variable time-delay between data-out from BRAM ;)

2) I have such log-information related to "fetch0" in {../synth_1/runme.log} file:

And no WARNING information about "fetch0" in {../impl_1/runme.log} file

My Vivado version is 2015.4:

So, could you please clarify you design situation -> is it my design from OpenCores SVN or your custom design (+ Vivado version)?

Warning nr 5: From Xilinx it is stated in ISE 14.7 the gprf0 memory is automatically initialized. So it should be okay. In core => fetch: Madd_r_program_counter[31]_GND_12_o_add_2_OUT1 output er connected to ground, I thought it was incrementing Mmux_fetch_comb.v_program_counter1 see thesis figure 3.7. I compared with your module mblite_unit, it is also connected to ground. Warning 1,2 and 4 I dont understand :( 1.HDLCompiler:746 -core_Address_Decoder_imem\mblite\std_Pkg.vhd" Line 260: Range is empty (null range) 2.HDLCompiler:220 -core_Address_Decoder_imem\mblite\std_Pkg.vhd" Line 260: Assignment ignored 3.Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. 4.Xst:2677 - Node of sequential type is unconnected in block . 5.PhysDesignRules:2410 - This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used. For more information, please reference Xilinx Answer Record 39999.

Hi kuzmi4! I am using my custom design with core gen memories for instruction and datamem. ISE Design Suite 14.7 is used. Little bit retro i know:) Are using makefile from Thesis and write data to wb_adapter addess.Next s_dmem_o(1)_dat_o are routed into a parallel to serial shift register where each bit of the 32 bit vector are sent to PMOD JA(0) out port. An oscilloscope is connected to JA(0) for verifying of functionality. Warning nr 5: From Xilinx it is stated in ISE 14.7 the gprf0 memory is automatically initialized. So it should be okay. In core => fetch: Madd_r_program_counter[31]_GND_12_o_add_2_OUT1 output er connected to ground, I thought it was incrementing Mmux_fetch_comb.v_program_counter1 see thesis figure 3.7. I compared with your module mblite_unit, it is also connected to ground. Warning 1,2 and 4 I dont understand :( 1.HDLCompiler:746 -core_Address_Decoder_imem\mblite\std_Pkg.vhd" Line 260: Range is empty (null range) 2.HDLCompiler:220 -core_Address_Decoder_imem\mblite\std_Pkg.vhd" Line 260: Assignment ignored 3.Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. 4.Xst:2677 - Node of sequential type is unconnected in block . 5.PhysDesignRules:2410 - This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used. For more information, please reference Xilinx Answer Record 39999.