Hi all,

I am interesting in generating a cycle accurate systemC module using the verilator tools. In fact, I installed and simulated the project ORPSoC. It generates a systemC module of the whole project. However, I am interested in having the ability to generate separately cycle accurate systemC modules for Openrisc 1000 and other components.

Could someone guide me how can I modify the compilation script to be able to compile and generate cycle accurate systemC modules for each component separately?

I appreciate each suggestion...

Have a look at the xge_mac project, it has quite a nice little verification testbench using verilated RTL and systemc modules:

http://opencores.org/ocsvn/xge_mac/xge_mac/trunk/

Hi ag09

If it helps you, there is an Embecosm App Note on building Verilator models, which uses OpenRISC as an example.

http://www.embecosm.com/download/ean6.html

HTH

Jeremy

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Hi Jeremy,

your above mentioned application note was my guide to that example and it was very useful.

I am now interesting in generating cycle accurate systemC module for each HW component to enable e.g. multi-level design.

I will look at the example that Julius sent to me. But if someone made any experience in this fields then I will be glad to get references to that works...

.

Hello all,
I want to convert verilog code to c language, and I tried to fellow the steps to get the conversion but my steps are incorrect. can anyone help me to convert a simple verilog code to c step by step.
Best,

If you just want a simple example of converting verilog to C++ (not C) using verilator, try looking at the rtcclock project. It's small, it's simple, and the verification is done for the rtcdate subproject using verilator to convert from verilog to C++.

To do it, there's a makefile in the rtl directory that converts the verilator to C++. Then, in the bench/cpp directory, there's another Makefile that can be used to build the rtcdate_tb test bench.

I think you'll find this approach a lot simpler than trying to build openrisc, but also that once you are done you will have resolved any implementation issues so that you can turn around and do openrisc should you wish to.

Dan

Hi,

You can take a look at how FuseSoC does that. Install fusesoc (https://github.com/olofk/fusesoc) and run fusesoc sim --sim=verilator mor1kx-generic to build a minimal SoC with an OpenRISC CPU, UART and RAM.

//Olof