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Verilog Compiler
by chinthakaak on Oct 3, 2009 |
chinthakaak
Posts: 4 Joined: Oct 1, 2009 Last seen: Dec 2, 2014 |
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Hi,
I am new to OpenCores. Could anyone please let me know whether is there specific opensource Verilog compiler we have to use in OpenCores projects? Regards, Chinthaka |
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RE: Verilog Compiler
by moogyd on Oct 8, 2009 |
moogyd
Posts: 15 Joined: Nov 22, 2008 Last seen: Jun 26, 2019 |
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Hi,
Any verilog simulator should work with OpenCores IP's. Icarus Verilog is open source, and seems to work OK http://www.icarus.com/eda/verilog/ Steven |
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RE: Verilog Compiler
by jeremybennett on Oct 9, 2009 |
jeremybennett
Posts: 815 Joined: May 29, 2008 Last seen: Jun 13, 2019 |
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I am new to OpenCores. Could anyone please let me know whether is there specific opensource Verilog compiler we have to use in OpenCores projects? Hi Chinthaka Since it is open source you can use whatever you wish. OpenRISC is verified with scripts written to use Icarus Verilog (free and open source) or Verilator (also free and open source). However in the past that project has used Cadence NC (proprietary), and I've seen it run with ARC VTOC (also proprietary).Other projects will have their own arrangements, but you can choose to verify or compile as suits your needs. Steven has given you a link to Icarus Verilog. For VHDL projects there is GHDL (ghdl.free.fr). Verilator (www.veripool.org/wiki/verilator is an open source synthesizable Verilog to C++/SystemC compiler, which delivers performance similar to commercial simulators. Embecosm has an application note explaining how to use Icarus Verilog and Verilator with OpenRISC, which you may find useful: High Performance SoC Modeling with Verilator. Hope this helps. Jeremy
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RE: Verilog Compiler
by chinthakaak on Oct 9, 2009 |
chinthakaak
Posts: 4 Joined: Oct 1, 2009 Last seen: Dec 2, 2014 |
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Hi Steven, Jeremy,
Thanks a lot for the responses. Regards, Chinthaka |
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