A-Z80 CPU :: Overview
Other project properties
Update: Rewritten in pure Verilog, the CPU can now be used on both Altera and Xilinx devices!
A-Z80 is a conceptual implementation of the venerable Zilog Z80 processor targeted to synthesize and run on a modern FPGA device. It differs from the existing (mostly Verilog) Z80 implementations in that it is designed from the ground-up through the schematics and low-level gates. It is a result of a research and tedious reverse-engineering of Z80 at all levels, including micro-photographs of a die.
Project includes a fully working Sinclair ZX Spectrum implementation based on this CPU.
It has been described in more details at BaltazarStudios.
- Cycle and bus accurate including the correct behavior of nWAIT and nBUSRQ
- All documented and undocumented opcodes, flags and registers, including R, WZ
- Following the actual arcitectural model down to the individual gates and registers for some modules
- Passes ZEXDOC and ZEXLL (except quirky OTIR/LDIR for IX,IY)
- Correct behavior of BIT n,(HL) to expose WZ
- All interrupts modes (IM0,IM1,IM2)
RTL SimulationDesign is simulated using ModelSim.
- Each module contains a ModelSim project
- Contain individual SystemVerilog test files
- Test wave (*.do) files to quickly set up views
There is a "quick" sanity test as well as a much longer comprehensive test.
Top-level SimulationZMAC assember is used to generate Z80 program test snippets which are then run in the simulation and on the actual FPGA hardware. The resulting files should match.
This level of tests adds UART to the ModelSim and FPGA implementation so the tests can be run and outputs compared.
- Tests for various complex instructions like DAA, NEG
- Classic "Hello, World" application
- Tests for interrupt behavior
- ...and more tests embedded in *.asm test files
ImplementationSeveral complete and working FPGA designs illustrate implementation and test the A-Z80 on both Altera and Xilinx devices:
- Basic Computer using keyboard and UART to run Z80 tests
- Complete implementation of a Sinclair ZX Spectrum
This design is fully completed, tested and working.
A Cyclone II based Altera DE1 board implementation used about 11% of its LE's.
A Spartan-6 based Nexys3 board implementation used about 19% of its slices.
This implementation is using free Altera and Xilinx tools (Quartus II v13.0.1 Web Edition and Xilinx ISE Webpack). It also uses Python 3.5 to build some components and tests.
Although based on Altera and Xilinx devices, this project could be used with other vendors since (Quartus-specific) schematic files are pre-compiled into generic Verilog files.