AES Decryption Core for FPGA
Project maintainers
Details
Created: Jan 30, 2014
Updated: May 7, 2015
SVN Updated: May 7, 2015
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Other project properties
Language:Verilog
Development status:Beta
Additional info:Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
While there are many AES cores around, this one is designed with LUT6 based FPGA architecture in mind from day one.
The AES Decryption Core for FPGA implements the decryption portion of the AES (a.k.a. Rijndael) algorithm described in the FIPS-197 specification. Key lengths of 128 / 192 / 256 bits are supported, each with a separate instantiation wrapper. Since the core is designed to take advantage of LUT6 based FPGA architecture, it packs very well in those devices. The result is a peak throughput of over 3Gbps for 256-bit key, yet occupies about 2000 LUTs only. The core has been verified with random test vectors as well as selected test vectors in FIPS-197, SP-800a, and AESAVS specifications. Self checking testbenches are included.
The core has been tested on Xilinx KC705 development board.
Benchmark numbers are shown below.
Xilinx Kintex xc7k325tffg900-3
| 128-bit | 192-bit | 256-bit | |
|---|---|---|---|
| LUT | 1865 | 2350 | 2033 |
| FF | 310 | 443 | 448 |
| BRAM | 0 | 0 | 0 |
| Latency w/ key switching | 22clk | 26clk | 30clk |
| Latency w/o key switching | 11clk | 13clk | 15clk |
| Fmax | 369MHz | 361MHz | 365MHz |
| Peak throughput | 4.293Gbps | 3.554Gbps | 3.114Gbps |
Xilinx Kintex UltraScale xcku040-ffva1156-2-e
| 128-bit | 192-bit | 256-bit | |
|---|---|---|---|
| LUT | 1791 | 2269 | 1969 |
| FF | 299 | 441 | 438 |
| BRAM | 0 | 0 | 0 |
| Latency w/ key switching | 22clk | 26clk | 30clk |
| Latency w/o key switching | 11clk | 13clk | 15clk |
| Fmax | 380MHz | 364MHz | 375MHz |
| Peak throughput | 4.421Gbps | 3.584Gbps | 3.200Gbps |