OpenCores

high throughput and low area aes core :: Overview

Details

Name: aes_highthroughput_lowarea
Created: Mar 3, 2010
Updated: Jan 1, 2011
SVN Updated: Jan 1, 2011
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Crypto core
Language: Verilog
Development status: Stable
Additional info: none
WishBone Compliant: No
License: LGPL

Description

This core can reach more than 2 Gbps throughput.
Gate count is around 35k.
Pipelined structure.
Core was successfully verified using FIPS KAT vectors (for ECB mode). The testbench is included with the project.

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