OpenCores

Aquarius :: Overview

Project maintainers

Details

Name: aquarius
Created: Jul 12, 2003
Updated: Jul 6, 2012
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Processor
Language: Verilog
Development status: Stable
Additional info: FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License: GPL

Description

Aquarius is a Core IP (Intellectual Property) of pipelined RISC CPU and can execute SuperH-2 instructions. Follows are SuperH characteristics.

- SuperH is a very popular CPU core. The software development environments such as C compiler have been well prepared. The GNU C compiler for SuperH is very famous and easy to get. The SuperH had been developed by Hitachi, Ltd. Now, semiconductor group of Hitachi has merged with same group of Mitsubish and new semiconductor company ?gRenesas Technology Corp.?h has established in April, 2003.
- SuperH-2 is a CPU for MCU (Micro Controller Unit). Then the CPU need not handle complex exception recovering such as memory fault exception from MMU (Memory Managing Unit). This means SuperH-2 has simple structure, easiness to design, and it does not consume many logic gates and power.
- All SuperH-2 instructions have 16bit length. It also makes the hardware very simple. And most important aspect from 16bit fixed length of instructions is that the object code size compiled from C source programs becomes very small.

Features

- Instruction set is compatible with SuperH-2.
- Bus interface is compatible with WISHBONE.
- Aquarius is written in Verilog RTL codes.
- Aquarius has verified on a test bench by vector simulation and FPGA implementation with GNU Assembler and C Compiler.
- Interrupts and Exceptions are fully supported.
- Low Power Mode (SLEEP) is supported.
- Some small applications are provided including debugging monitor for a FPGA board.
- A complete Document with over 100 pages, describing Usage of Aquarius, FPGA Implementation and Inside Aquarius, is provided.

IMAGE: cpublock.gif

FILE: cpublock.gif
DESCRIPTION: CPU Block Diagram

Inside CPU

Top layer of Aquarius is ?gCPU?h which has WISHBONE compliant bus signals and accepts interruption related signals. The most important system signals such as clock and reset are not shown in this figure.

The Memory Access Controller handles instruction fetch and data read/write access. The operations of Memory Access Controller are fully controlled by Decoder unit. Memory Access Controller sends fetched instruction bit fields to the Decoder unit, and interchanges read/write data and its address with Data Path unit. Aquarius assumes the Wishbone bus is a Non-Harvard bus, then the simultaneous instruction fetch and R/W data access makes bus contention. Memory Access Controller handles such contention smoothly and informs the pipeline stall caused by the bus contention to Decoder unit. Also, the Memory Access Controller can sense each boundary of bus cycles (with wait state) from WISHBONE ACK signal. In Aquarius architecture (may be in SuperH-2 architecture as well), such bus cycle boundary corresponds to the pipeline?fs slot edge. So the Memory Access Controller produces the most important pipeline control signal ?gSLOT?h indicating pipeline slot edge.

The Data Path unit has registers you can see in programmer?fs model in SuperH-2 manual such as General Registers (R0 to R15), Status Register (SR), Global Base Register (GBR), Vector Base Register (VBR), Procedure Register (PR) and Program Counter (PC). The Multiplication and Accumulate Registers (MACH/MACL) are found in Multiplication unit. The Data Path unit also has necessity operation resources such as ALU (Arithmetic and Logical operation Unit), Shifter, Divider, Comparator, temporary registers, many selectors, interfaces to/from Memory Access Controller and Multiply unit, and several buses to connect each resource. The Data Path is fully controlled by control signals from Decoder unit.

Multiplication unit has a 32bit x 16bit multiplier and its control circuits. A 16bit x 16bit multiplication operation is executed in one clock cycle. A 32 bit x 32bit multiplication operation is done in two clock cycles. Multiplication unit also has the Multiplier and Accumulate Registers (MACH/MACL). The MACH/MACL are not only the final result registers of multiply or multiply-and-accumulation but also the temporary registers to hold the 48bit partial multiply result from 32bit x 16bit multiplier for 32bit x 32bit operation. The multiply instruction, for example MULS.L, clears the contents of MACH/MACL in early stage of the instruction operation. However the multiply and accumulate instruction, for example MAC.L, does not clear MACH/MACL before the operation. The MAC.L accumulates its own partial multiply result to initial MACH/MACL and then finalize the operation result. The major difference between multiply (MULS.L) and ?gmultiply and accumulate?h (MAC.L) is whether to clear or not to clear the MACH/MACL before the operation. And also, for MAC.L and MAC.W instruction, the accumulation adder in this unit has saturating function.

The Decoder unit is the fundamental CPU controller. It orders Memory Access Controller fetch instructions and then receives the instruction. The Decoder Unit decodes the instruction bit fields and judges the followed operations. Basically, the Decoder unit plays the role only for the instruction ID stage. But it throws many control signals for following EX, MA and WB stages toward Data Path unit, Multiplication unit, and Memory Access Controller. These control signals are kept and shifted with its pipeline flow at each slot edge until reaching to the target stage of the instruction. The Decoder unit detects every conditions of pipeline stalling, and makes each unit of CPU be controlled properly. Also, it controls not only simple 1 cycle instructions but also multi cycle instructions and exception?fs sequences such as interrupt and address error.

Status

- RTL coding and verifying have already been finished.
- FPGA (Xilinx VirtexE) implementation with LCD, Matrix Keyboard and RS-232C interfaces has also finished using GNU Assembler and C Compiler.
- Some small Applications using FPGA and its interface board have finished.
- Detail Design Document has finished.

Deliverables

- Verilog RTL codes for CPU, and Test Bench including modules comprising MCU, such as UART, System Controller, Parallel I/O Interface, and Internal Memories (ROM/RAM).
- Verification Resources, such as Converter from S-format to Verilog format for ROM coding, and Assemble Source Programs for Vector Simulation.
- FPGA Resources, such as Circuit Schematics of Interface Board, Converter from S-format to Xilinx BlockRAM INIT statements for RAM initialization, and a sample of User Constraints File.
- Small Applications written in C Sources including LCD Test Program, Clock using interval interrupt, Debugging Monitor, and Calculation of Circular Constant (Pi).

IMAGE: rtl.gif

FILE: rtl.gif
DESCRIPTION: Tree of RTL

Download

Documents, RTL Source codes and related Tools can be downloaded from the OpenCores CVS; the directory is "Aquarius".

Performance

Aquarius CPU core and related peripheral modules have been configured in both Xilinx and Altera. Following table shows their performance.

FPGA Device

Performance(cpu.v)

Xilinx VirtexE (XCV300E) 2753 slices @21MHz
Altera Stratix (EP1S10) 7499 cells @31MHz

IMAGE: fpgaboard.gif

FILE: fpgaboard.gif
DESCRIPTION: FPGA Board

© copyright 1999-2017 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.