Computer Operating Properly :: Overview
Project maintainers
Details
Name: cop
Created: May 23, 2009
Updated: Jan 27, 2010
SVN Updated: Sep 17, 2011
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: Other
Language: Verilog
Development status: Beta
Additional info:
Design done, Specification done
WishBone Compliant: Yes
License: BSD
Description
The Computer Operating Properly Module, COP, is a watchdog timer module that triggers a system reset if it is not regularly serviced by writing two specific words to its control registers. The intention of the module is to bring an embedded system back to a “good” state after the software program has lost control of the system.