cpu6502_tc - R6502 Processor Soft Core with accurate timing

Description

This is a VHDL IP core with True Cycle Timing for Rockwell's 6502 8-Bit CPU (Verilog is no longer available). With full functional input signals like ready, interrupt, non maskable interrupt and set overflow flag. Also available is the output signal sync which signals an op fetch. The ready signal is usable for DMA operations or multiprocessing. Signal sync can be used for software/hardware debugging via single stepping (single cycles or complete op codes) the 6502.
This core was successfully tested in an APPLE ][+ SoC (completely designed into a FPGA with Z80 Softcard, DISK2 System, 80C Card, Language Card and 48kB of main memory).

Please feel free to contact me for any reasons like ideas or error messages.

Features

- true cycle timing for all official opcodes
- unknown op's decoded as "NOP/0xEA"
- one clock source
- input signal "rdy_i" for generating waitstates (see original documentation of R6502)
- output signal "sync_o" to indicate an op fetch (see original documentation of R6502)
- input signal "so_n_i" sets the internal OV Flag (see original documentation of R6502)
- fully synthesizable VHDL and Verilog

Status

CORE: Ready for use and downloadable
LICENSE: Puplished under GPL V3
DOCUMENTATION: "done"
TESTBENCHES: "ready"
TESTSOFTWARE: "ready"

QUALITY:
- all op codes: simulated and approved under real working conditions (APPLE ][plus SoC)
"PASSED" in Klaus Dormann's Test Suite and Bruce Clark's Decimal Test
- irq_n_i: simulated and run in real environment
"PASSED" in Klaus Dormann's Test Suite
- nmi_n_i: simulated and run in real environment
"PASSED" in Klaus Dormann's Test Suite
- so_n_i: only simulated
- all other signals: simulated and approved under real working conditions (APPLE ][plus SoC)

History:
Revision 1.4 2018/09/15 22:07:00 jens
- RESET generates SYNC now, 1 dead cycle delayed
- ADC / SBC flags and A like R6502 now
- Bug Fix ADC and SBC in decimal mode
(all address modes - "Overflow" flag was computed wrong)
- Interrupt priority order is now: BRK - NMI - IRQ
- Performance improvements on-going (Mealy -> Moore)
- Bug Fixes All Branch Instructions
(BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS)
3 cycles now if branch forward occur and
the branch instruction lies on a xxFEh location.
- Bug Fix Hardware Interrupts NMI & IRQ - "SYNC" now

(Sep-13-2018)
- Added assembler test routines from Klaus Dormann & Bruce Clark
- Added ERRATA file for reported requests and bugs.

(Mar-15-2010)
- Correct interrupt sequences for NMI and IRQ

(Feb-25-2009)
- Correct "RTI" (wrong: use of stack pointer)
- Rename all states of "FSM Execution Unit" for better reading
- Update HTML documentation
- (90%) Finish working for Specification of cpu6502_tc

(Jan-09-2009)
- Phaze 2: Remove unused nets, registers and modules
- Added Verilog source files on demand by customers (for trial use)

(Jan-04-2009)
- Remove unused nets, registers and modules
- Update HTML documentation to visualize the Execution unit

(Apr-17-2008)
- State of project
- CVS loaded with new core and HTML documentation
- correct the handling of the stack while BRK, IRQ and NMI
- correct the handling of "B" flag while BRK
- correct the alignment between addresses and data while BRK, IRQ and NMI when writing onto the stack