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cpu65c02_tc - R65C02 Processor Soft Core with accurate timing :: Overview

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Details

Name: cpu65c02_true_cycle
Created: Apr 12, 2008
Updated: Aug 2, 2013
SVN Updated: Aug 2, 2013
SVN: Browse
Latest version: download
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Other project properties

Category: Processor
Language: VHDL
Development status: Stable
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
License: GPL

Description

The 65C02 by Rockwell is the upgraded version of the legendary Rockwell's R6502. cpu65c02_tc offers you an accurate timing for all new and upgraded op codes of the R65C02. This soft core was generated in VHDL and was designed with Mentor's HDL Designer.
It comes also with graphical views formatted in HTML to show and explain very clearly the hierarchy of the whole design.

Please feel free to tell me any ideas, errors or some thing else like special functions, test benches or documentation. Use the "Tracker" link to do this.

Features

- true cycle timing for all official opcodes
- unknown op's decoded as "NOP/special op codes"
- one clock source
- input signal "rdy_i" for generating waitstates (see attached specification of R65C02)
- output signal "sync_o" to indicate an op fetch (see attached specification of R65C02)
- input signal "so_n_i" sets the internal OV Flag (see attached specification of R65C02)
- fully synthesizable VHDL

Status

- Based on the cpu6502_tc core
- This version will support Rockwell's 65C02 (other variants are planed for future)
- Core is running in a APPLE //e SoC and tested under ProDOS V2.0.3 and
Klaus Dormann's 6502/65c02 test suite written in assembler.

CORE: "READY - RELEASE CANDIDATE"
LICENSE: Puplished under GPL V3
DOCUMENTATION: "on working"
TESTBENCHES: "on working"
TESTSOFTWARE: "ready"

QUALITY:
- all of the new R65C02 op codes are tested under real working conditions with
Klaus Dormann's 6502/65c02 test suite written in assembler (included in /asm now)
- irq_n_i: not fully tested on real hardware yet
- nmi_n_i: not fully tested on real hardware yet
- so_n_i: not fully tested on real hardware yet

History

Aug-02-2013
Revision 1.5 RC 2013/07/31 11:53:00 (RELEASE CANDIDATE)
- Bug Fix CMP (IND) - wrongly decoded as function AND
- Bug Fix BRK should clear decimal flag in P Reg
- Bug Fix JMP (ABS,X) - Low Address outputted twice - no High Address
- Bug Fix Unknown Ops - Used always 1b2c NOP ($EA) - new NOPs created
- Bug Fix DECIMAL ADC and SBC (all op codes - "C" flag was computed wrong)
- Bug Fix INC/DEC ABS,X - N/Z flag wrongly computed
- Bug Fix RTI - should increment stack pointer
- Bug Fix "E" & "B" flags (Bits 5 & 4) - should be always "1" in P Reg. Change "RES", "RTI", "IRQ" & "NMI" substates.
- Bug Fix ADC and SBC (all sub codes - "Overflow" flag was computed wrong)
- Bug Fix RMB, SMB Bug - Bit position decoded wrong
Revision 1.4 2013/07/21 11:11:00 (internal copy only - not published)
- Changing the title block and internal revision history
- Bug Fix STA [(IND)] op$92 ($92 was missed in the connection list at state FETCH)

Feb-25-2009
- Correct "RTI" (wrong: use of stack pointer)
- Correct "RMBx" & "SMBx" (wrong: bit translation)
- Rename all states of "FSM Execution Unit" for better reading
- (85%) Finish working for Specification of cpu65C02_tc
- Correct timing for addressing mode "ABS,X" for "INC" (wrong: 6 cycles instead of 7)
- Optimize end states of "STA" (s197,s207,s200,s213)

Jan-04-2009
- Deleted unused/duplicated nets, registers and modules. Renamed some blocks. Synthesis run now without warnings.

Dec-01-2008
- CVS loaded with updated finite state machine (bug fixes for interrupts)
- Include an example for specification (copied from cpu6502_tc - on working)

Aug-05-2008
- CVS loaded with BETA source files (VHDL)

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