I2C controller core :: Overview
Project maintainers
Details
Name: i2c
Created: Sep 25, 2001
Updated: Apr 25, 2013
SVN Updated: Jun 6, 2010
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: Communication controller
Language: Verilog
Development status: Stable
Additional info:
ASIC proven, Design done, FPGA proven, Specification done
WishBone Compliant: Yes
License: BSD
Description
I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the consumer and telecom market sector and as a board level communications protocol. The OpenCores I2C Master Core provides an interface between a Wishbone Master and an I2C bus. It is an easy path to add I2C capabilities to any Wishbone compatible system. You can find the I2C specifications on Phillips web Site. Work was originally started by Frédéric Renet. You can find his webpage here.
Features
- Compatible with Philips I2C bus standard
- Multi-Master Operation
- Software programmable timing
- Clock stretching and wait state generation
- Interrupt or bit-polling driven byte-by-byte data-transfers
- Arbitration lost interrupt, with automatic transfer cancelation
- (Repeated)Start/Stop signal generation/detection
- Bus busy detection
- Supports 7 and 10bit addressing
- Fully static and synchronous design
- Fully synthesisable
Documentation
- Revision 0.8 of the WISHBONE I2C Master Core specifications are available here. - Also see the FAQ page.
Status
- Design is available in VHDL and Verilog from OpenCores SVN via this link