minsoc :: Overview
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Name: minsoc
Created: Sep 18, 2009
Updated: Jun 17, 2010
SVN Updated: Jun 17, 2010
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: SoC
Language: Verilog
Development status: Stable
Additional info:
Design done, FPGA proven, Specification done
WishBone Compliant: Yes
License: LGPL
Description
The Minimal OpenRISC System on Chip is a System-on-Chip (SoC) implementation with standard IP cores available at OpenCores. This implementation consists of a standard project, comprehending the standard IP cores necessary for a SoC embedding the OpenRISC implementation or1200.
This project idea is to offer a SoC, which can be uploaded to every FPGA and be compatible with every FPGA board, without the requirement of changing its code. In order to deliver such a project, the project has been based on a standard memory implementation and the Advanced Debug System, which allows system debug with the same cables used for FPGA configuration.
The adaptation of the project to a target board is made in 2 steps maximum. First the minsoc_defines.v file has to be adjusted, generally one has to only uncomment his FPGA manufacturer and FPGA model definitions. After that a constraint file for your specific pinout has to be created. There are constraint files for standard boards also, in the backend directory of the project.
Furthermore the project offers for this same SoC a working testbench and firmwares. The actual testbench can be run out of the box using Icarus Verilog v. 9.1. The firmwares are nearly the same of those of orpsocv2. The differences are for now, that the known uart "hello world" example now runs with interrupts and a new Ethernet example has been added to it.
To complete, the size of the standard memory of the implementation can be adapted to your needs/possibilities by defining its address width inside of the same minsoc_defines.v file.
An overview about the complete SoC and its external connections is on Figure 1.
System Features
-or1200 OpenRISC implementation
-Resizable onchip memory
-System frequency selection
-JTAG debug featuring a multitude of cables
-Start-up option to automatically load your firmware on start-up from an external SPI memory
-UART and Ethernet modules
-FPGA independent and dependent code (Xilinx & Altera) for memory, clock adaptation (PLLs and DCMs) and JTAG Tap
-System configuration in a single definition file
-Example firmwares using UART and Ethernet
-Testbench included, for the simulation of exacly your configured system
Status
All minsoc FPGA indenpendent features have been simulated and proven to work.
The FPGA independent features have been tested on an FPGA implementation and are working. These comprehend the FPGA independent only modules, start-up, Ethernet, UART and or1200 OpenRISC; and the generic JTAG tap and the generic clock divider. The latters can be either FPGA dependent or independent. On the other hand, the generic memory cannot be implemented in an FPGA independent way, because the synthesizer does not allocate them to RAMs, consuming then all FPGA flip-flops.
The FPGA dependent features, onchip memory, clock frequency adaptation and JTAG taps have to be tested for different FPGAs. Xilinx implementations differs in both instantiation and implementation for all modules. Altera differs perhaps in implementation, but the modules can be instantiated equally. For now there is no specific implementation of a clock frequency adaptation PLL for Altera, since a nice verilog instantiation of an Altera PLL has not been found yet.
Test of FPGA dependent features requires feedback from users, for now we have positive results from the following configurations:
-Xilinx, Spartan 3E (Spartan3E Starter Kit) (Thanks to Bakiri Mohammed)
-Xilinx, Spartan 3A (Spartan3A 1800 DSP Kit)
-Xilinx, Virtex 4 (ML405 board) (Thanks to Ravi Kumar)
-Altera, Cyclone II (Thanks to Nathan Yawn)
-Altera, Stratix II
For now no configurations have been proven not to work.
To Do
Version 1.0:
-Optimize and complete the testbench: Ethernet and UART interface control from testbench is still very poor. Furthermore the Ethernet testbench manages somehow to decrease the simulation speed by factor 300, so this has to be improved. [100%]
-Write documentation explaining the system, its modules and connections. Include future steps, what to do after successfully running minsoc. [100%]
-Create an instantiation of a generic Altera PLL for the clock adaptation module. [0%]
Version 1.1:
-Include new communication controllers and develop drivers for them: I2C and CAN have been already successfully implemented for minsoc but still have to be seamless integrated to the definition file in order to be de- or activated without harming the system. I2C, CAN and an improved Ethernet driver have also been programmed and are in the queue to join the project. [70%]
-Substitute the minsoc_tc_top.v for wb_conbus or wb_conmax for either simplicity or performance (shared-bus or switch). [0%]
-Include further memory interface controllers to be selected by the configuration system, SRAM, DDR, DDR2. [0%]
-Extend system configuration to software configuration. Amount of memory and memory space (base address of modules) should be automatically updated to the software headers, orp.ld and board.h to avoid configuration errors. The same way, deactivated modules should remove the respective addresses definitions from the headers so that compilation errors arise when using non-existent modules. [0%]