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*NEO430 Processor (MSP430-compatible) :: Overview

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Details

Name: neo430
Created: Oct 16, 2015
Updated: Jul 20, 2017
SVN Updated: Jul 20, 2017
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Processor
Language: VHDL
Development status: Stable
Additional info: Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: LGPL

Description

Welcome to the NEO430 processor project! - Now also hosted on github!

You need a small but still powerful, customizable and microcontroller-like processor system for your next FPGA design? Then the NEO430 is the perfect choice for you!

This processor is based on the Texas Instruments MSP430 ISA and provides 100% compatibility with the original instruction set. The NEO430 is not an MSP430 clone – it is more a complete new implementation from the bottom up. The processor features a very small outline, already implementing standard features like a timer, a watchdog, UART and SPI serial interfaces, general purpose IO ports, an internal bootloader and of course internal memory for program code and data. All of the peripheral modules are optional – so if you do not need them, you can exclude them from implementation to reduce the size of the system. Any additional modules, which make a more customized system, can be connected via a Wishbone-compatible bus interface. By this, you can built a system, that perfectly fits your needs.

It is up to you to use the NEO430 as stand-alone, configurable and extensible microcontroller, or to include it as controller within a more complex SoC design.

The high-level software development is based on the free TI msp430-gcc compiler tool chain. You can either use Windows or Linux/Cygwin as build environment for your applications – the project comes with build scripts for both worlds. The example folder of this project features several demo programs, from which you can start creating your own NEO430 applications.

This project is intended to work "out of the box". Just synthesize the test setup from this project, upload it to your FPGA board of choice and start exploring the capabilities of the NEO430 processor. Application program generation (and even installation) works by executing a single "make" command.

NEO430 Overview
NEO430 block diagram, optional modules
are marked using dashed lines
The NEO430 processor features separated internal memories for data and instructions. The size of the instruction memory (IMEM) can be configured to a maximal size of 32kB. This memory can either be implemented as RAM, allowing you to upload new application programs at any time using the bootloader. Also, this bootloader allows to fetch an application image from an external SPI EEPROM at system start-up. By this, you have the advantage of a re-programmable but non-volatile program storage. The internal data memory (DMEM) can have a size of up to 28kB. This program space is used for variables and of course for the heap and the stack of your program. All peripheral devices are memory-mapped and require a special linker script and dedicated C include files to be accessed. Therefore, you need to recompile your programs with the supplied tool chain to make them run on the NEO430. NEO430 Memory Layout
NEO430 address space layout


For more information about this project and step-by-step tutorials, check out the NEO430 Processor Documentary!


Processor Features

  • Open source 16-bit (data and addresses) soft-core processor
  • Very small hardware outline compared to other implementations ;)
  • Full support of the original TI(TM) MSP430 instruction set architecture (ISA) (remove the 's' in https if the page is not loading...)
  • Multi-cycle instruction execution (4..12 cycles per instruction)
  • Software development based on free TI msp430-gcc compiler (remove the 's' in https if the page is not loading...)
  • Application compilation scripts for Windows and Linux/Cygwin
  • C libraries for easy usage of the included hardware modules
  • Execute a single "make" to install your application into the processor's instruction ROM
  • Standard C libraries (like stdlib.c) can be included
  • Many example programs
  • RTL design completely written in behavioral, platform-independent VHDL
  • Exemplary Wishbone memory and switching fabric VHDL components for creating your SoC
  • FPGA-proven design, operating at very high clock speeds
  • Single clock domain for complete processor
  • One user-defined external interrupt request lines
  • Customize the design: Select which optional HW units will be implemented
  • Several integrated modules:
    • Internal instruction memory (IMEM), ROM or RAM, up to 32kB
    • Internal data memory (DMEM), RAM, up to 24kB
    • System information memory (IMEM and DMEM size, clock speed, HW features, ...)
    • Optional high precision timer
    • Optional custom function unit (CFU) to attach custom memory-mapped function
    • Optional USART/USI (highly configurable, independent UART and SPI modules)
    • Optional parallel GPIO port (16xIN and 16xOUT) with pin-change interrupt
    • Optional Wishbone bus interface (standard and pipelined transfers) to attach custom IP blocks
    • Optional watchdog timer
    • Optional internal bootloader (2kB ROM):
      • Upload program via UART
      • Boot from external SPI EEPROM (like 25LC512)
      • Program the external SPI EEPROM with a boot image
      • Automatic boot process (e.g. no user interaction required to boot from EEPROM)
      • Core hex dump (for debugging or just to see what's going on)
      • Self-explaining serial text console interface

Status

  • Processor is fully synthesizable (FPGA platform independent)
  • All system modules have been verified
  • Bootloader operates properly and is capable of transferring & booting program images
  • C standard libraries can be included (to use atoi, sprintf, ..., even floats! ;) )
  • Example folder provides a lot of tested and properly working demo programs
  • Application (compilation) make files for Windows and Linux/Cygwin
  • Step-by-step tutorials for setting up your first NEO430 project
  • Testbench with UART RX terminal emulation; waveform configuration for Xilinx ISIM simulator
  • Tutorials for nearly everything =)
  • Example Wishbone RAM/ROM and switching fabric included (VHDL files)
  • Processor has been verified using the example programs, an FFT application and also a custom mp3-player (SD-card, FAT32, VS1053, ...)
  • Had to remove MSPGCC support, because this tool has severe bugs
TODO:
  • Get benchmark performance results (CoreMark? Dhrystone? Custom?!?!)
  • Since the address space of the neo430 is different to the original msp430 address space, I had to remove the hardware multiplier for now (hopefully I am able to fix this issue)

Implementation Results - Default (Full) Configuration

The following implementation results were generated using the full default configuration of the NEO430 (neo430_top.vhd):

  • IMEM: 4kB (default)
  • DMEM: 2kB (default)
  • Internal bootloader: Included
  • Wishbone bus adapter (WB32): Included
  • Parallel IO (PIO): Included
  • Serial interfaces (USART): Included
  • High-precision timer (TIMER): Included
  • Watchdog timer (WDT): Included
  • DADD instruction: Included
Intel Quartus Prime 16.1 fitter results ("balanced implementation") for an Altera Cyclone IV FPGA (Terasic DE0-Nano board):
Altera Cyclone IV EP4CE22F17C6N
Total logic elements:1188 / 22320 = 5%
Dedicated logic registers:556 / 22320 = 2%
Total memory bits:70016 / 608256 = 11%
9-bit multiplier:0 / 132 = 0%
Maximum Frequency:116 MHz*
*) "Slow 1200mV 0C Model"
Data generated for processor version 0x0100 (26th of November, 2016)
ISE 14.7 mapping results ("speed-optimized") for a Xilinx Virtex-6 FPGA:
Xilinx Virtex-6 XC6VLX240T-2FF1156
Number of 6-input LUTs:811 / 150720 = >1%
Number of Slice Registers:676 / 301440 = >1%
Number of Block RAMS:4 / 832 = >1%
Number of DSP48E1s:0 / 768 = 0%
Maximum Frequency:174 MHz*
*) Synthesis result
Data generated for processor version 0x0100 (9th of December, 2016)

Implementation Results - Custom Configuration

The following implementation results were generated using a customized configuration (for a SoC) of the NEO430 (neo430_top.vhd):

  • IMEM: 2kB
  • DMEM: 2kB (default)
  • Internal bootloader: Included
  • Wishbone bus adapter (WB32): Included
  • Parallel IO (PIO): Included
  • Serial interfaces (USART): Included
  • High-precision timer (TIMER): Included
  • Watchdog timer (WDT): Included
  • DADD instruction: Included
  • Additional features: Wishbone EFB interface and Wishbone switching fabric
Lattice Diamond 3.7.1.502 implementation results for a Lattice MachXO2-1200ZE FPGA (MachXO2 Pico Development Kit):
Lattice MachXO2 MACHXO2-1200ZE
Number of LUT4s:1096 / 1280 = 86%
Number of registers:519 / 1595 = 33%
Number of block RAMs:6 / 7 = 86%
Maximum Frequency:12.09 MHz*
*) Constrained
Data generated for processor version 0x0091 (5th of November, 2016)

Implementation Results - By Entity

Intel Quartus Prime 16.1 fitter results ("balanced implementation") for the default configuration for an Altera Cyclone IV FPGA (Terasic DE0-Nano board). These values give a very rough overview of the ressource requirements of each entity.

Entity / ModuleLEsFFsMEM bitsDSPsFunction
CPU*:5781892560Central processing unit: the heart of the processor
IMEM* (4kB):41327680Instruction memory
DMEM* (2kB):41163850Data memory
Sysconfig*:891280Contains read-only information about the processor configuration
Bootloader ROM (2kB):11204800Bootloader program storage (2kB, non-volatile, read-only)
PIO:27440016 input and 16 output IO ports
WDT:463400Watchdog timer
TIMER:825500High-precision timer
USART:16012400Configurable SPI and UART serial interfaces
WB32:607600Wishbone-comptaible bus interface
*) Mandatory entity
Data generated for processor version 0x0100 (26th of November, 2016)

Contact

If you have any questions about the NEO430 or if you want to give any kind of feedback, feel free to drop me some lines ;)

  • E-mail: stnolting@gmail.com
This project is also hosted on github.

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