Open8 uRISC

8-bit RISC processor core for creating highly customizable microcontroller systems

The Open8 uRISC CPU started out as a "clean" reimplementation of the Vautomation uRISC processor core (aka the "V8", also named the Arclite core) based on ISA documentation only. Over the years, it has grown into a substantially different CPU, though the core ISA is still largely backwards compatible.

* Thirty-six basic instructions (and four new instructions)
* 8-bit PSR(Program Status Register) with Zero, Carry, Negative, and Interrupt status bits, and 4 general purpose status bits.
* Eight 8-bit registers, R0 though R7.
* Accumulator register (R0)
* A 16-bit program counter
* Any two adjacent registers may be paired to create a 16-bit index register.
* Three basic addressing modes; addressed, indexed, and indexed with offset

The design adds a few new features, which can be enabled through generics:
* An optional auto-increment for indexed addressing modes ("LDX R4++" is equivalent to "LDX R4 ; UPP R4" )
* A new branching instruction, DBNZ (Decrement, and Branch if Not Zero)
* A new math instruction, MUL, uses on-board multipliers.
* The interrupt mask can now be set with the new instructions SMSK and GMSK
* A generic has been added to alter the ROL/ROR instructions to ignore the carry, allowing them to operate as normally anticipated.
* The RSP instruction may now optionally be converted into a "relocate SP" instruction with the ability to copy between R1:R0 <> SP based on the state of PSR_GP4, which has been aliased as PSR_S.
* A "Supervisor mode" was added that restricts access to certain instructions to only execute when the I bit is set. This prevents tasks from inadvertently executing privileged instructions, such as RSP. This is also used to enforce memory write protection if implemented.

The Open8 is being designed to work optimally in newer FPGA architectures. It assumes 2 clocks for memory and register file latency.

Features

- Model is written in VHDL ('93)
- Simple RISC architecture and instruction set. All instructions fit in a single byte, with either 1 or 2 operands.
- 16-bit PC / address allows for 64kB of directly accessible memory (can be expanded with paging) - Flat memory model allows code or data to be placed anywhere in the memory map, as well as easily supporting self-modifying code.
- Moderate number of general purpose registers
+ Eight byte-wide registers.
+ Any two registers may be paired as (Rn+1:Rn) to create an index register
+ R0 acts as the accumulator
- 8 interrupts, 1 NMI, 7 maskable. Interrupt controller is built into the core.
+ Interrupt controller keeps track of interrupt priority
+ Interrupt mask is controllable through two new instructions, SMSK and GMSK.
- Reasonably small gate-count, with strong fMax in "low-end" devices.

Status

* The CPU is being used in a system that requires real task switching, so the ability to optionally alter the RSP (reset stack point) so that it behaves as a Retrieve/Relocate Stack Pointer was added. This has been tested in a real design and works well - though writing the task switching code is really an eye-opener on context switching costs. (This particular device has 7 asynchronous tasks) The entire SoC takes about 8% of a Cyclone EP4CE22 and runs at 120MHz.

* In the past, this design has been fielded as a test stimulus controller hosted, which has performed without hiccup for several years now. This system required some advanced math that would have been slow to implement in pure assembly, so a 16-bit ALU/co-processor was written to "hardware accelerate" common math functions, rather than have to write emulations in assembly. This ALU has been included in the SVN repository. The Open8, and its ALU coprocessor, use about 2400 LE's in the FPGA.

* Several other generally useful entities have been added to the repository such as a simple serial port, HD44780 character LCD controller, system timer, real-time clock, and a memory-mapped SDLC interface. These may be broken out as separate projects at some point, but they all are written around the Open8 CPU / bus interface.