OpenRISC 1000
Project maintainers
- Kamath, Anantha
- Kim, SungSU
- Scrivano, Giuseppe
- Bennett, Jeremy
- Bonn, Jonas
- Baxter, Julius
- Erlandsson, Marcus
- Admin, OpenCores
- Kindgren, Olof
- Anastasiadis, Nikolaos
- Gavin, Peter
- D'Addio, Rich
- Herveille, Richard
- Fielding, Steve
- Horne, Stafford
- Skrzypek, Piotr
- Kristiansson, Stefan
- Edvardsson, Adam
- Markovic, Tadej
- Unneback, Michael
- Vernier, Yann
Details
Name: or1k
Created: Sep 25, 2001
Updated: Jan 31, 2019
SVN Updated: Apr 28, 2018
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 166 reported / 166 solved
Created: Sep 25, 2001
Updated: Jan 31, 2019
SVN Updated: Apr 28, 2018
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 166 reported / 166 solved
Star25you like it: star it!
Other project properties
Category:Processor
Language:Verilog
Development status:Stable
Additional info:ASIC proven, Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Stable
Additional info:ASIC proven, Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
Status of the OpenRISC 1000
WARNING!
The development of the OpenRISC moved to OpenRISC.io
The files contained in this repository are most likely outdated.
For more information try to get in contact with one of the former developers (project maintainer).
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