OpenCores

PIF2WB :: Overview

Project maintainers

Details

Name: pif2wb
Created: Aug 4, 2007
Updated: Aug 7, 2007
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: System on Chip
Language: VHDL
Development status: Beta
Additional info: Design done, Specification done
WishBone Compliant: Yes
License:

Description

This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.

Features

- PIF master support
- Wishbone slave support
- Burst transfers support
- VHDL RTL
- Fully synthesisable

Status

- RTL: Complete
- Document: Complete

© copyright 1999-2017 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.