Reed-Solomon Codec Generator :: Overview
Project maintainers
Details
Name: reed_solomon_codec_generator
Created: Jul 21, 2011
Updated: Aug 8, 2012
SVN Updated: Jul 28, 2011
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: ECC core
Language: Verilog
Development status: Stable
Additional info:
Design done, FPGA proven, Specification done
WishBone Compliant: No
License: LGPL
Description
This tool working on WinXP is used to generate verilog-RTL for Reed-Solomon Codec. - Selectable Decoder/Encoder/Both - Symbol width 3,4,5,6,7,8,9,10,11 - Primitive polynomial - Erasure Enable/Disable - Configurable Data I/F - Automatically available testbench - Distributed under the GPL license If you need more customize or hi-performance IP, please let us know. info@syslsi.com